搜索资源列表
asynchronous-FIFO-verilog
- FIFO是英文First In First Out 的缩写,是一种先进先出的数据缓存器,他与普通存储器的区别是没有外部读写地址线,这样使用起来非常简单-FIFO is an abbreviation of the English First In First Out, is a first-in, first-out data buffer, the difference between him and ordinary memory is external read and write add
FIFO
- 三种同步方式实现的FIFO,verilog HDL,FPGA,更好理解FIFO-The three implemented synchronously FIFO, Verilog HDL, FPGA, a better understanding of the FIFO
synchronous-FIFO
- 同步fifo的使用verilog案例讲解-The use of synchronous fifo verilog case to explain
async_fifo-and-verilog
- 异步fifo的详细原理分析说明及verilog源代码,经典推荐!-Detailed descr iption of the principles and analysis of asynchronous fifo verilog source code, the classic recommendation!
fifo
- 一个经典的fifo的Verilog工程实例,相信对初学者会有一定的帮助。-A classic instance of fifo Verilog project, I believe there will be some help for beginners.
FIFO(verilog)
- FIFO 的verilog代码,包含测试源码,可以参考学习FIFO的编写-FIFO written with verilog
asyn_fifo
- 该源码包是异步fifo的Verilog语言模型,主要包括2个部分:异步fifo控制模块、测试文件。(The source package is asynchronous FIFO Verilog language model, including 2 main parts: asynchronous FIFO control module, test files.)
syn_fifo
- 该源码包是同步fifo的Verilog语言模型,主要包括2个部分:同步fifo控制模块、测试文件。(The source package is a synchronous FIFO Verilog language model, including 2 main parts: synchronous FIFO control module, test files.)
FIFO
- 用verilog语言的实现FIFO存储器,以先进先出的方式处理数据(The FIFO memory is implemented in Verilog language, and data is processed in FIFO)
sp6ex19
- FPGA片内FIFO实例,对FPGA片内FIFO进行读写测试(FPGA examples of FIFO, FPGA on-chip FIFO reading and writing test)
asyn_fifo_204b_28
- 通用性异步fifo,性能非常好,推荐给大家(unverisal asyn fifo)
eetop.cn_FIFO_Buffer
- 异步FIFO的Verilog程序及其测试程序(FPGA/Verilog FIFO_ASYN)
fifo
- fifo in qurtuas using verilog
fifo
- 基于verilog HDL的fifo设计与测试,包含设计与测试代码,以及简单的makefile编写。整个平台是基于linux操作,仿真平台是基于SYNOPSYS的vcs工具。(Based on verilog HDL fifo design and testing, including the design and test code, and simple makefile.The platform is based on Linux operating, the simulation pla
FIFO
- FIFO code in verilog
异步FIFO
- 自己编写的同步和异步FIFO的verilog代码,验证过,有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)
FIFO
- FPGA片内FIFO实例,对FPGA片内FIFO进行读写测试(FPGA FIFO example, reading and writing FIFO in FPGA chip.)
fifo
- Verilog HDL实现通用的FIFO的一个demo,可以参考这个程序根据自己的需求更改深度和宽度,以及标志位(Verilog HDL implements a demo of a generic FIFO that you can refer to to to change the depth and width, as well as the flag bits, depending on your needs)
verilog实例 [43项]
- 一些采用verilog描述的数字功能模块,有常见的同步异步FIFO,RAM等模块,适合新手学习(Some digital function modules described by Verilog, such as synchronous asynchronous FIFO and ram, are suitable for novice learning)
异步FIFO
- 纯Verilog实现的异步FIFO,分为读写控制模块,SRAM CORE,同步等几个模块,内含源文件和仿真文件(The asynchronous FIFO implemented by Verilog is divided into read-write control module, SRAM core module and synchronization module)