搜索资源列表
FIFO
- 基于FPGA的FIFO控制器的设计与实现，ISE，verilog-FPGA-based design and implementation of FIFO controller, ISE, verilog
asfifodesign
- 异步fifo设计文档，里面包括详细的verilog设计方案及代码。fifo设计是通信中必然设计的设计-a fifo design with code inside, using verilog language
fifolifo
- fifo filo verilog 程序！先入先出数据存储器的程序和先入后出程序！-fifo filo verilog program! First in first out data memory of the program!
fifo
- 基于verilog的异步fifo设计，仿真效果良好-asynchronous fifo based on zhe verilog language
ad_da_ctr
- 基于FPGA的ad和da转换Verilog代码，FPGA采用ep2c5芯片，做成异步fifo，ad芯片采用TI的ths1230,da芯片采用TI的TLV5619，仿真结果基本正确。-FPGA-based ad and da conversion Verilog code, FPGA using ep2c5 chip, made ??of asynchronous fifo, ad-chip using TI s ths1230, da chip uses TI s TLV5619, simula
sdh
- SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
USB_Interface
- verilog USB USB的slave fifo的控制-verilog USB
ref-sdr-sdram-verilog
- SDRAM的vegilog代码，做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM
VGA-VerilogHDL
- 用Verilog HDL编写的VGA显示驱动程序-Verilog HDL prepared with VGA display driver
FIFO1
- FIFO存储电路的设计与实现，用verilog实现fifo的参考设计-FIFO memory circuit design and realization of the realization of fifo with Verilog reference design
fifo
- 先入先出缓冲存储器，采用verilog hdl-FIFO buffer memory, using verilog hdl
fifo
- 可综合的Verilog FIFO存储器. This example describes a synthesizable implementation of a FIFO. -Can be integrated Verilog FIFO memory. This example describes a synthesizable implementation of a FIFO.
fifo
- 先进先出缓存器的verilog设计与实现-design of fifo(first in first out)
fifo
- 实现fifo的基本功能。使用Verilog能够实现的同步数据先入先出功能，简单易懂，并带有相应的测试文件-Fifo realize the basic functions. Be able to use the Verilog implementation of the synchronous data FIFO functions, easy to understand, with the corresponding test file
cfifo_ptrs_binary
- system verilog fifo env
ASYNCFIFO
- 异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现-asynchronous fifo
8fifo
- 可综合的 8x8 fifo VHDL 源代码-Can be integrated 8x8 fifo VHDL source code
FIFO
- 利用Verilog实现了一个FIFO，包含几个模块文件，适合初学Verilog的朋友，含测试代码。-Verilog achieved using a FIFO, a document contains several modules, suitable for novice Verilog friends, including test code.
fifo_test
- FIFO读写verilog程序，经本人验证，能够顺利运行。实现FPGA对fifo的控制。-the example of writing and reading the fifo ram of the fpag,i have already tested it.
parallel-fifo
- 利用Verilog语言编写的并行数据传输程序，在编译环境中编译通过。- the model of parallel data transmit which is written of verilog.