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VHDL_FIR_PRO_scr.rar
- 可编程的FIR滤波器VHDL实现，只要输入FIR的阶数以及系数，就可在FPGA中实现FIR滤波器,Programmable FIR filter VHDL implementation, simply enter the order number as well as the FIR coefficients, we can implement FIR filters in FPGA
LMS_filter
- verilog HDL 写的LMS滤波器-LMS filter using verilog HDL language
FIR_Direkt_ak
- VHDL代码的直接型FIR滤波器22阶。Fa=48 kHz, Fc=10kHz 可以在ModelSim下仿真， FPGA实现。 -VHDL code of the direct-type 22-order FIR filter. Fa = 48 kHz, Fc = 10kHz can be under the ModelSim simulation, FPGA realization.
fir_lms
- 基于FPGA的自适应滤波器的实现。采用Verilog编程，2阶滤波器。-FPGA-based realization of the adaptive filter. Using Verilog programming, 2-order filter.
firshuzilvboqi
- :介绍了基于FPGA的FIR数字滤波器的设计与实现,该设计利用Matlab工具箱设计窗函数计算FIR滤波器系数,并通过VHDL层次化设计方法,同时FPGA与单片机有机结合,采用C51及VHDL语言模块化的设计思想及进行优化编程,有效实现了键盘可设置参数及LCD显示。结果表明此实现结构能进一步完善数据的快速处理和有效控制,提高了设计的灵活性、可靠性和功能的可扩展性。 -: This paper presents FPGA-based FIR digital filter design and
fir5k
- 通带为4500到5500的带通fir的VHDL程序，经实践检验可用-Passband for the 4500-5500 bandpass fir of VHDL procedures, can be used by the practice
VHDL_TipsTricks
- 一个FIR的vhdl基本设计介绍，优化。代码与图文相互对应，简单易懂-introduction to VHDL design with codes related to optimized circuit.
sdram_vhd
- FPGA设计的SDRAM控制器，有仿真代码，已通过验证-FPGA Design of SDRAM controller, there is simulation code has been validated
IIR
- 毕业设计：基于FPGA的IIR滤波器设计-The design for IIR digital filter based on FPGA
FIR_Direkt_BAB_P
- VHDL编写的代码。采用流水线方法实现的FIR滤波器。22阶。Fa=48kHz, Fc=10KHz。可用ModeSim仿真并FPGA实现-Code written in VHDL. Line method using the FIR filter. 22 bands. Fa = 48kHz, Fc = 10KHz. Can be used to achieve ModeSim simulation and FPGA
filtru_fi
- This is a filter fir implemeted in vhdl, i hope it will work :)
fir8
- 用verilog编写的8阶串行fir滤波器-verilog vhdl fir
17firvhdl
- 基于FPGA的17阶FIR滤波器VHDL代码及说明文档-fpga fir
fir_filter_generator_latest[1].tar
- C语言编写的FIR数字滤波器自动生成VHDL代码-fir_filter_generator_VHDL
Finiteimpulseresponsefirfilter
- This code is a VHDL based code for FIR filter.A finite impulse response (FIR ) filter is a type of a digital filter. The impulse response, the filter s response to a Kronecker delta input, is finite because it settles to zero in a finite number of sa
f
- vhdl code for FIR filter
hdlsrc
- vhdl program to implement symmetric fir filter
fir_sig
- 直接型FIR滤波器，VHDL语言，程序结构简单，-A direct-type FIR filters, VHDL language, program structure is simple,
FIRFIR1
- 基于FPGA的FIR串行滤波器设计与实现，本文运用VHDL编写-FPGA-based FIR filter design and implementation of the serial, the paper prepared by the use of VHDL