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lcd_12864
- 本历程使用FPGA根据LCD12864的时序图编译成功的可以显示汉字、字母数字的VHDL程序-The process of using the FPGA timing chart compiled according to LCD12864 success can display Chinese characters, alphanumeric VHDL program
timing
- Video RGB timing搭配FPGA系統及三色LED控制,可以實現色序法(Field sequential display).-Video RGB timing with FPGA and three-color LED control system can achieve color sequential (Field sequential display).
div_frequency
- 任意分频器，用Verilog HDL实现，只需修改参数可以实现奇数、偶数分频，FPGA应用必备资料。-Any divider, using Verilog HDL to achieve, simply modify the parameters can be achieved odd, even frequency, FPGA applications necessary information.
31241213verilog_uart_NO
- FPGA串口通讯例程，经我修改绝对可用； 默认48M,9600-8-1/2，如果时钟不同只需修改时钟分频数即可。-The FPGA serial interface communication by the modified routine, absolute can be used The default 48 M, 9600-8-1/2, if the clock different modify it only clock points frequency can.
weitb
- 在数字通信中，通常直接从接收到的数字信号中提取位同步信号，这种直接法按其提取同步信号的方式，大致可分为滤波法和锁相法。锁相法是指利用锁相环来提取位同步信号的方法，本设计方案就是基于锁相环的位同步提取方法，能够比较快速地提取位同步时钟，并且设计简单，方便修改参数。采用Quartus II设计软件对系统进行了仿真试验，并用Altera的Cyclone II系列FPGA芯片Ep2c5予以实现。-In digital communication, usually from receiving direc
fpgaconvert
- 将xilinx 的fpga配置bit文件转换为c语言文件，通过cpu配置fpga-translate？i can t
AD_TEST
- 1、 本工程主要是把输人AD芯片的电压显示在数码管上。 2、 测试时，从JTAG口把AD_TEST.sof下载到FPGA，右边的4个数码管将会显示电压数据（单位：毫伏）。 -1, this project is mainly to AD input voltage displayed on the digital chip tube. 2 test, from the JTAG port to AD_TEST.sof download to the FPGA, the right o
task2
- Verilog语言，可在QuartusII正确运行，实现远程控制系统，利用异步串行通信，PC发送数据FPGA接收，实现本地回环模式。-清华大学电子课程设计：Verilog language, you can QuartusII correctly, remote control systems, using asynchronous serial communication, PC to send data received FPGA to achieve the local loopback
task22constant
- 清华大学电子课程设计：Verilog语言，Quartus可以正确运行，下载到FPGA上可完成PC与FPGA一串数据的连续收发，且实现本地回环，异步串口通信-Verilog language, Quartus can be correctly downloaded to the FPGA to be completed by PC and FPGA transceivers continuous string of data, and implement local loop, asynchron
washing-machine-control
- 基于VHDL的洗衣机洗涤控制电路设计。洗衣机有强洗、标准、轻柔三种洗涤模式；三种洗涤定时；上电复位后的初始设定；启/停控制；洗涤定时精度。可在FPGA上实现。-VHDL-based washing machine control circuit design. Washing machine to wash with strong, standards, gentle washing three kinds of models three kinds of washing time afte
xiaodou_fpga
- fpga的按键消抖程序，用硬件描述语言实现，可以用在按键控制的fpga上。-fpga key debounce procedure, using hardware descr iption language, can be used in the control buttons on the fpga.
FPGA_IO
- Experience counts – especially when engineering the right FPGA solution. And with more than 50 years of experience, Acromag can help you reduce your costs and increase your productivity.-Experience counts- especially when engineeri
my_VGA
- FPGA驱动VGA显示，通过验证，需要的可以下载。verilog实现-VGA display driven by the FPGA, through validation, need can be downloaded. verilog implementation
13-45
- 本程序能够完成的功能是，自动或手动测温，读取配置寄存器，温度下限寄存器，温度上限寄存器，设定温度上限及下限，当温度到达预定的温度的时候报警。所有的读取操作都可以在数码管上显示。其中，温度的上限通过计算机用串口通信协议传输给FPGA内部寄存器然后按动开关写入。同时，本程序还驱动了一个直流电机，温度高的时候电机转速高，温度低的时候转速降低直至停转。数码管可以实时显示电机转速，2秒刷新一次。数码管的显示可以在显示的温度、寄存器值和直流电机转速间切换，切换通过串口进行，计算机发00H时切换到温度及寄存器
QuartusII
- ALter官方FFt程序，代码通过下载到fpga上可以通过。-ALter official FFt program code can be download to fpga through.
FPGA_FIDOandSPI
- 在FPGA中建立一个FIFO可用宇内部传输测试使用，也可以用于两个单片机之间的数据传输，同时还上传了基于DSP的SPI设置的FPGA源码-Create a FIFO in the FPGA internal transmission test using the available buildings, can also be used for data transfer between two microcontrollers, but also upload a set of DSP-bas
test8
- 这是一个Verilog编写的VGA驱动程序，该程序在FPGA开发板上运行后，能在VGA显示上显示一个行走人的动画-This is a VGA driver in Verilog, the program running in the FPGA development board can display a person s walking animation on a VGA display。
digital-clock
- 该程序是有verilog实现的fpga的交通灯 适用于cycloneII芯片 可供fpga初学者学习verilog语言时参考，不仅可以显示时钟 还能调整时钟分针秒针-The program is a verilog realize fpga of traffic light is applicable to cycloneII chips available for beginners to learn verilog fpga languages as reference, not only
anylist-exam
- 任意模计数器FPGA程序代码设计，可实现模1000以内的任意模，更改参数可提高范围-Any mold counter FPGA code design, model 1000 can be achieved within any mode, change the parameters can increase the range
anymode
- 任意模计数FPGA程序代码设计，可以输入任意模值，并由数码管显示计数，-Count any FPGA code design mode, you can enter any model values by digital display counts,