搜索资源列表
Altera_IPcore
- 15个Altera ip核，大家可以相爱在使用-15 Altera ip
pc_cfr_v2_0_msim_r2_0
- Xilinx公司pc_cfr IP核的MatLab仿真-matlab simulation model of pc_cfr ip core of xilinx
fftip
- 2008-2009年优秀硕士论文之：基于FPGA的高性能32位浮点FFT IP核的开发-Outstanding Master' s thesis 2008-2009: FPGA-based high-performance 32-bit floating-point FFT IP core development
fpga-jianpan-ip-core
- 基于fpga的键盘设计ip核的vhdl源代码-Ip fpga design of the keyboard based on the vhdl source code for nuclear
ethernet10-100M-IP-core
- 以太网10-100M IP核Verilog源码，可综合-Ethernet 10-100M IP core Verilog source code can be integrated
USB-1.1-IP-CORE-VHDL
- USB1.1标准接口的IP核的实现和其设计实现的源码范例VHDL-USB1.1 standard interface IP core implementations and examples of their design and implementation of the VHDL source code
ise-ip-core
- IP核包括硬IP与软IP。调用IP核能避免重复劳动，大大减轻设计人员的工作量。-IP cores, including hard IP and soft IP. IP calls to avoid duplication of nuclear energy, thus greatly reducing the workload of the designer.
vga_lcd
- VGA/LCD控制 ip核，支持 CRT LCD,支持多种色彩方案。-VGA/LCD control ip core, support CRT LCD, supports a variety of color schemes.
xapp1052
- ML605开发版 生成IP核的时候选择250MHZ pcie2.0 X4 5Gb/s 其他参考PDF文档。(When the ML605 development version generates the IP kernel, select 250MHZ pcie2.0 X4 5Gb/s Other reference PDF documents.)
ip核
- 购买的beckoff公司的ip核，提供了详细的datasheet以及协议说明，附上调用ip核的文件，采用verilog编写，平台可以在ISE里自己设置(Buy the beckoff company's ip kernel, provides a detailed datasheet and protocol descr iption, attached to the ip kernel file, using verilog prepared, the platform can be set
ROM_test
- 使用quartus调用ROM的IP核，并生成激励文件进行仿真(Use the quartus call ROM IP kernel, and generate incentive files for simulation.)
FSK
- 首先利用IP核记录sin和con波形，然后进行FSK调制，信息为数字信息(Firstly, the IP kernel is used to record the sin and con waveforms, and then the FSK is modulated, and the information is digital information)
dac_controller
- 以ip核的形式来控制数模转换芯片，减少cup开支。(dac controller ip /dac controller)
simon_IP
- 实现总线加密或解密的IP核（APB总线）（含tb测试平台）(Realization of encryption and decryption of IP core (APB bus))
iir_2n_ip_float_demo
- 使用altera提供的ip核，实现了浮点数运算的2阶iir滤波器，结果与matlab运算结果相同。(Using the IP core provided by Altera, the 2 order IIR filter of floating point operation is implemented, and the result is the same as that of MATLAB operation.)
USB2.0的IP核（详细verilog源码和文档）
- USB2.0的IP核（详细verilog源码和文档）.rar
基于xilinx ip 核的千兆以太网代码
- 基于xilinx ip 核的千兆以太网代码，利用tri_mode_ethernet_mac实现了千兆以太网的数据收发
HDMI编码ip核
- verilog语言编程，HDMI解码输出ip核
pynq的h264 demo 开源的复旦h264 ip核
- pynq的h264 demo 开源的复旦h264 ip核
ip核
- softing网站的有关altera的EtherCAT ip核相关资料