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19_ethernet_test_RGMII
- 以太网FPGA程序 verilog ise开发(ethernet_test_RGMIIx verilog)
Multiplier
- fpga门电路实现的8位乘法器, verilog 语言编写，ise平台(implementation of multipler)
FIR
- FIR filter in verilog for xilinx ise design suit
CPU
- 语言为verilog，平台是ISE，指令较少。32位MIPScpu，可以直接运行(The language is Verilog, the platform is ISE, and the instructions are fewer. 32 bit MIPScpu, can run directly)
Data_watch
- 用Verilog开发，ISE平台打开，开发板采用Xlinx公司的N4开发板，该数字钟集计时、闹钟、整点报时、12 24进制切换等功能于一体(Developed by Verilog, the ISE platform is opened, and the development board is developed by Xlinx's N4 development board. The digital clock integrates functions such as timing, ala
AlteraLab1
- To design Fibonacci Sequence using Verilog. SOFTWARES USED: Xilinx Synthesis Tool ISE 9.2i INTRODUCTION. Hardware descr iption language (HDL) is a general-purpose language intended to describe circuits textually,
myClock
- 四位数码管显示24小时时钟，附上了ucf 芯片是Kintex7(Four bit digital tubes display 24 hour clocks)
Design
- 利用Xilinx ISE用Verilog编写的计算器(Using Xilinx ISEalculator and register heap program written in Verilog HDL language)
图像中值滤波FPGA实现V1.0
- 实现图像的中值滤波功能，文件里有效果展示(The realization of the median filter function of the image, the file has the effect of display)
74HC4511 7段显示译码器
- 译码器，七段显示译码器，内含波形图，测试代码和源码，以及.v文件，verilog编写，ise平台运行(Decoder, seven segment display decoder, contain waveform, test code and source code, as well as.V file, Verilog writing, ISE platform running)
好-无线通信FPGA设计-Xilinx
- 《无线通信FPGA设计》以Xilinx公司的FPGA开发平台为基础，综合FPGA和无线通信技术两个方向，通过大量的FPGA开发实例，较为详尽地描述了无线通信中常用模块的原理和实现流程，包括数字信号处理基础、数字滤波器、多速率信号处理、数字调制与解调、信道编码、系统同步、自适应滤波算法、最佳接收机，以及WCDMA系统的关键技术。《无线通信FPGA设计》概念明确、思路清晰，追求全面、系统、实用，使读者能够在较短的时间内具备无线通信领域的FPGA开发能力。(The design of wireless