搜索资源列表
Turbo VHDL
- VHDL源程序
turbo码 IP core
- turbo码 IP core, VHDL编写,Altera公司的,用于信道编码中turbo码的译码
RSC.rar
- Turbo码编码器的两个分量编码器RSC,主要由四个移位寄存器和两个模2加法器组成,Turbo code encoder of the two component encoders RSC, mainly by the four shift register and the two-mode adder composed of 2
turbo
- turbo的VHDL代码 比较好啊 易后大家多多交流啊-Comparison of the VHDL code for turbo Well you lot of the easy exchange of ah
turbocodes_latest.tar
- turbo encode and decoder
turbo_VHDL
- Turbo码的VHDL描述,可以下载下来-VHDL descr iption of Turbo Codes
turbodecoder
- 用vhdl实现turbo码的迭代解码,转某N人的程序-Using vhdl implementation of iterative decoding turbo codes, transfer of a person' s procedures for N
Turbo
- 基于fpga的交织编码器设计,主要讲叙如何在fpga上实现交织编码器。-something about turbo。
control
- Turbo码编码器时序控制模块,能够对于RAM,ROM读写以及编码器其他功能模块的使能进行控制-Turbo code encoder timing control module, to the RAM, ROM reader and encoder modules, other functions can be controlled so that
delete
- Turbo码编码器的删除模块,此模块是CCSDS标准系的码率为1/2和1/3的删除模块-Turbo code encoder to delete module, this module is the Department of CCSDS standard rate of 1/2 and 1/3 of the delete module
encode_finish
- Turbo码编码器的encode最上层模块,它的主要作用是连接Turbo码编码器的其他模块-Turbo code encoder encode top-level module, its main role is to connect the Turbo Code encoder other modules
rom
- Turbo码编码器的Rom宏模块,此模块中包含Rom.v文件和存储交织地址的.mif文件-Turbo code encoder Rom macro module, this module contains intertwined Rom.v documents and store addresses. Mif file
ram255x8
- A Basic ram structure with 256 data handling
EnergyEfficientVLSIArchitectureforLinearTurboEqua
- Energy efficient for turbo encoder decoder
IterativeDecodingofBinary
- In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and deco
MapAlgorithm
- However, turbo equalizers can be computationally complex and hence require significant power consumption. In this paper, we present an energy-efficient VLSI architecture for such linear turbo equalizers. Key architectural techniques include elimi
VerilogLangRefManual
- Simulation results show that energy savings in the range 30–60 and 10–60 are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an efficient rescaling metho
jiaozhiqi
- 是Turbo码交织器的VHDL设计与仿真的文献-Is the Turbo Code Interleaver Design and Simulation of VHDL literature
turbo
- Turbo仿真。VHDL语言。对学习编码很有帮助-Turbo
tpc
- turbo product code used in error correction