搜索资源列表
VHD
- 此为基于Xilinx的FPGA用VHDL实现的FIFO,已调通,可直接运行。-This is based on Xilinx FPGA using VHDL implementation of the FIFO, has been transferred through, can be directly run.
SDRAM
- sdram,在fpga数据传递领域应用广泛,乒乓操作,不同频域的数据传递,都靠sdram来转换。-SDRAM VHDL FPGA FIFO
61i_async_fifo_v5_1_vhdl
- VHDL Code for FIFO+coregen v5.0
fifo8x8
- fifo 8x8 vhdl fifo_array is array(7 downto 0) of std_logic_vector with flag --Full fifo-- --half fifo-- --empty fifo-fifo 8x8 vhdl fifo_array is array(7 downto 0) of std_logic_vector with flag --Full fifo-- --half fifo-- --empty
asdhbja
- 异步FIFO源代码 vhdl基于FPGA的设计,绝对值得一下,非常不给力的20 个字-vhdl code of asynchronous FIFo
FIFO_TD
- FIFO的VHDL测试程序,在Modelsim下完全可以运行-The test_bench of fifo
fifo_module
- 基于vhdl的FIFO建模,主要是用于输入输出数据缓存-Vhdl-based FIFO modeling is mainly used for input and output data cache
12345
- 用vhdl编写的带fifo的uart,西电自动化系的作业-The vhdl write uart with fifo
MCTP1
- Vhdl 同步FIFO设计 该FIFO 实现方案比传统方式简单,工作速度频率高-Vhdl synchronous FIFO design of the FIFO implementations simpler than traditional, high working speed frequency
aFifo
- Function : Asynchronous FIFO VHDL CODE
Ram_FIFO
- VHDL硬件语言实现FIFO,管道,经过测试,很好用-VHDL hardware language FIFO, pipe
syn_fifo
- 同步FIFO源代码,使用Verilog编写,用户可以轻松转换成VHDL。-Synchronized FIFO source code
3333333
- 基于vhdl语言的同步fifo的宏模块调用程序,可学习fpga的宏模块调用方法-Synchronous fifo vhdl language-based macro block the calling program, can learn fpga macro module calls methods
syn_fifo_use
- fpga 同步fifo调用 vhdl语言编写syn fifo use -synchronous fifo call fpga vhdl language syn fifo use
xfft_v3_2_pipe_64
- vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband-vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband
t4_fifo
- FIFO的verilog与VHDL的实现,并与FIFO的IP核做对比,为了方便大家学习,每个文件均附有测试脚本文件,希望对大家有用。-The FIFO verilog and VHDL implementation with FIFO IP core to do comparison, in order to facilitate learning, each file with a test scr ipt file, we want to be useful.
UART_FIFO
- 用VHDL语言实现内置FIFO的UART,并做时序仿真和功能仿真确定正确与否。-Implement a built in FIFO UART using VHDL language, and do functional simulation and timing simulation to determine correct.
usb_packet_fifo
- usb packet fifo VHDL
asyn_FIFO-
- A asynchronous FIFO is implemented. VHDL fil+ vsim.do scr ipt
TransfData
- 用于FPGA发送数据,采用VHDL语言编程,采用16位fifo发送,内涵时钟、复位、使能信号-FPGA is used to send data, using VHDL language programming, using 16 fifo sent connotation clock, reset, enable signal