搜索资源列表
uart-verilog-vhdl
- 拿verilog和vhdl编写的串口通信代码(可综合)-with vhdl and verilog prepared by the serial communication code (synthesis)
UART
- 自己用VHDL写的一个串口程序,调试成功,并且用到了项目中,希望初学者可以借鉴下
uart
- 串口通讯协议,你您可以自己建个工程,再将需要的VHDL文本,添加到工程中,理解程序在仿真!
UART
- 通用UART串口的VHDL描述,可自行设定奇偶校验,波特率等参数-VHDL descr iption of generic UART serial port, they are free to set parity, baud rate and other parameters
uart1
- RS232(UART)串口传输,通过了FPGA验证功能正确-UART RS232 verilog HDL FPGA xilinx
UART
- uart 串口实现例程 VHDL语言实现-uart serial interface routines VHDL language
UART
- VHDL语言写的串口发送、接收程序,根据晶振和相应的波特率修改分频器就可以实现!-Written in VHDL serial send, receive, process, according to crystal and the corresponding baud rate divider changes can be achieved!
sci_module
- verilog编写的串口模块,可以直接使用,已经成功用于产品上了。-UART by verilog.
UART
- 用VHDL实现与电脑串口进行通信。已通过开发板验证正确。开发板时钟50M,波特率19200.-VHDL implementation using serial communication with the computer. Has been verified through the development board are correct.
uart
- FPGA基于串口指令的多电机闭环调速系统-FPGA based multi-port instruction Motor Closed Loop System
UART
- 串口VHDL程序,Xilinxṩ 测试成功。-Serial VHDL program, Xilinxṩ test was successful.
uart
- uart串口通讯,波特率任意可调,采用vhdl语言编写,ise和quartus均可使用-uart serial communication baud rate of any adjustable
VHDL-uart
- 本程序应用VHDL语言,详细描述了RS232串口协议,包括发送,接收,波特率的产生,模块化编程,对于初学者尤为有宜!-The program in VHDL language, the detailed descr iption of the RS232 serial protocol, including sending, receiving, and baud rate generation, modular programming, especially for beginners sho
UART
- 用VHDL书写串口通信源码,在fpga上验证过-Serial communication with VHDL source code written in the fpga verified
kehshechenxu
- 编制一全双工UART电路,通过试验箱MAX202E转换成RS232电平,与计算机进行通讯实验,设置8个按键,按键值为ASIC码“1”~“8”,通过串口发送给计算机,在计算机上显示键值,同时在数码管最高位显示;计算机可发送“0”~“F”的ASIC码,FPGA接收后在数码管低位显示0~F。通过按键可设置波特率。 要求:波特率为三种 1200、2400、9600,由1个按键选择,3个LED分别指示; 数据格式为1位起始位、8位数据位和一位停止位; 上位计算机发送接收软件可使用
用FPGA实现UART
- 用fpga实现异步串行通信。通过串口助手接收与发送(Implementation of serial communication with FPGA)
UAET_323_to_flow_led
- VHDL 实现串口收发并点亮流水灯,仿真成功(VHDL realizes serial port transceiver and lighting water lamp)
uart_txd
- 用VHDL实现的串口数据发送模块。使用的软件为ISE和modelsim。(Serial data transmission module implemented with VHDL.The software used is ISE and modelsim.)
uart
- RS232通信程序,用于实现PC端与FPGA之间实现串口通信(RS232 communication program for realizing serial port communication between PC and FPGA)
teacher_uart
- 由verilog编写的uart收发模块,能够在串口助手发送字符,并在数码管上显示,开发板为basys3 内置约束文件(The UART transceiver module written by Verilog can send characters to serial assistant and display them on the digital tube. the development board is built-in constraint file of basys3)