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mcst
- 曼彻斯特编码实现，verilog HDL 做的，我也是从网上下的-Manchester encoding to achieve, verilog HDL to do, I am also from the Internet under
multiply
- Verilog hdl语言 常用乘法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used multiplier design, can use the ModelSim simulation
1602
- verilog HDL语言编写的完整工程，功能是点亮1602lcd，在lcd上显示英文和数字-verilog HDL languages complete works, the functions of light 1602lcd, in the lcd display in English and the number of
Verilog-SRAM
- 用verilog hdl语言编写的fpga与片外sram 的读写控制-With the verilog hdl language fpga sram chip with read and write control
spi_verilog
- SPI协议Verilog HDL程序，内含testbench 文件
verilog
- 基于Verilog HDL的通信系统设计一书的电子教案，里面有很多例子，大家可以参考一下-Verilog HDL-based communication system design e-book lesson plans, there are many examples we can refer to
Verilog.HDL.Experiment
- Verilog.HDL.Experiment.例程-Verilog.HDL.Experiment. Routine
source3-6
- verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，3-6章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 3-6
VerilogHDL
- verilog hdl 综合实用教程，一本非常实用易学易懂的书-verilog hdl Comprehensive practical tutorial, a very useful book to learn to understand
shuzizhong
- 设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。 实验平台： 1. 一台PC机； 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, d
4weishuzipinlvjikongzhimokuai
- Verilog HDL下的4 位数字频率计控制模块源代码-Verilog HDL under four digital frequency meter control module source code
Verilog_HDL
- Verilog HDL程序设计教程,以可综合的设计为重点，同时对仿真和模拟也作了深入阐述。全面介绍了verilog HdL 词法，语法。-Verilog HDL Programming Guide, to be designed as an integrated focus on simulation and simulation at the same time also made to describe further. Verilog HdL gave a comprehensive ac
divide
- Verilog hdl语言的常用除法器设计，可使用modelsim进行仿真-Commonly used languages Verilog hdl divider design, can use the ModelSim simulation
VerilogHDL-huawei
- Verilog HDL 华为入门教程.pdf 内部资料-Verilog HDL Tutorial Huawei. Pdf internal information
traffic
- Verilog HDL语言设计的交通灯设计-Verilog HDL language designed traffic light design
Verilog_HDL_language_learning
- Verilog HDL语言练习与讲解 里面有很多实用的源代码-Verilog HDL language exercises on the inside and have a lot of useful source code
VerilogHDL
- Verilog HDL 华为入门教程-网络上比较经典的学习资料-Verilog HDL Tutorial Huawei- Network Learn more classical information
HuaweiFPGAdesignflowguide
- 华为内部的FPGA设计培训教程，详细阐述了设计流程图、Verilog HDL设计、逻辑仿真、逻辑综合。对大家的学习一定有帮助的。-Huawei within the FPGA design training tutorial, a detailed flow chart of the design, Verilog HDL design, logic simulation, logic synthesis. Study of the U.S. must have help.
16bitCLA
- 基于Verilog HDL的16位超前进位加法器 分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules
traffic
- verilog HDl 交通灯的实现,而且这是有别于一般的vhdl语言-verilog HDl traffic light