搜索资源列表
yibu_FIFO_design
- 异步FIFO实例，精通verilog hdl中的例子，供大家学习-Asynchronous FIFO instance, in the example verilog hdl proficiency for all learning
pal_vedio
- 基于FPGA的pal制模拟视频显示程序，verilog Hdl-pal-d vedio display fpga verilog
add_tree_mult
- 8位加法树乘法器,实现两个8位二进制数相乘，采用verilog hdl-8-bit adder tree multiplier, the achievement of the two 8-bit binary number multiplied, using verilog hdl
i8255_verilog
- 8255的Verilog hdl源代码，适合FPGA工程师使用-8255' s Verilog hdl source code for FPGA engineers
FPGA_AD7822
- 基于FPGA的AD转换控制器设计，AD7822，quartus II，verilog hdl-A Design of the A/D Convertion Control Module Based on FPGA
ddsVHDL
- fpga实例 包含很多使用的例子 累加器 乘法器 触发器等-FPGA example real Verilog HDL
Verilog-HDL-intra_prediction
- 基于H.264的帧内预测中4×4块的9种预测方法的源程序-H.264 intra prediction based on 4 × 4 block prediction method of the source 9
d_e_g_dds
- 基于Verilog HDL的迟早门码元同步方案中的DDS程序，已经仿真通过，可以在FPGA开发板上实现。迟-早门方式实现码元同步在无线通信中有着广泛应用。来自华中科大。-Early-later gate of Verilog HDL-based symbol synchronization scheme in the DDS program, has been through simulation, can be achieved in the FPGA development board. F
cmultip
- 用VERILOG HDL 实现节省乘法器的16位复数乘法器-With VERILOG HDL achieve savings of 16-bit complex multiplier multiplier
softdrink_testbench
- 一种可应用于自动售货机的状态机的verilog HDL描述-Verilog HDL descr iption of a state machine used in vending machines
divider
- verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。-verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.
crc7_4
- 使用Verilog HDL语言按标准编写的CRC（7,4）循环码，对学习编码有很好的指导作用！-Verilog HDL CRC(7,4) coding
verilogclk
- Verilog HDL语言编写的多功能数字钟.-Verilog HDL language multi-function digital clock.
all
- 基于FPGA的频率测试器的verilog HDL代码，测试范围1-10MHz，用XILINX公司的ISE软件打开。-Based on FPGA-frequency test the Verilog HDL code, test range 1-10MHz, with XILINX ISE software to open.
VerilogHDL
- 用Verilog HDL语言编写的跑马灯小程序，可直接在FPGA上运行-With the Verilog HDL language of the Marquee applet can be run directly on the FPGA
LCD1602
- 用VERILOG HDL编写的LCD1602例程，很好用，欢迎指点-LCD1602 routines, written in VERILOG HDL useful, welcome advice
RISC
- hrisc cpu，为何只有vhdl选择呢？大家都用verilog的啊-hrisc cpu why only VHDL choice? We all use the Verilog ah
VERILOGHDL
- this a book about the verilog-hdl design and circuit simulation and synthesize example
Serial
- FPGA与PC串口通信的Verilog HDL 程序-FPGA and the PC serial communication procedures Verilog HDL
jsq
- 本程序为24小时计时器，稳定无误差。简单好用，是Verilog HDL语言初学者的指引。-This procedure for 24-hour timer, stable error-free. Easy-to-use, is the Verilog HDL language beginners guide.