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learn_RS_coding
- 自己根据网上已有程序改写的(127,115)RS编码,有详细的注释及对FPGA实现算法的改写(参考try123.m),希望可以让大家少走弯路-(127,115) rs encoder/decorder with detailed annotations.
LIP1201CORE_dll
- Verilog DLL sOURCE CODE
JPEG2000
- jpeg 2000 encoder complete document
Encoder_SSI_Veryilog
- 本文详细描述了SSI协议的通讯格式、原理及应用电路,并采用verilog语言实现了SSI通讯协议.设计实用电路并实现了与绝对值编码器的通讯-SSI protocol described in detail the communication format, principle and application circuit, and use verilog language of the SSI protocol. Practical circuit design and implementat
video_from_opencore
- 全电视信号编码器,verilog的,看看有借鉴价值否?-video signal encoder, Verilog, to see whether the reference value?
rs-codec-8-16
- RS[255,223]纠错码verilog源码,包含编码和解码模块,以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
s_UIC_v3.03.tar
- (IBM) Interrupter Controller for PowePC405 (verilog)
encoder
- the encoder are designed to two for switchcase and if else function in verilog
pci_23
- this is 1553B encoder logic writen in verilog. is compatible with 1553 DDC
ldpc_encoder_802_3an_latest.tar
- 适用于10GBase-T的以太网(802.3an协议)LDPC, VERILOG语言编写,可以应用在LATTICEXP2系列芯片上,基于Gallager算法。-LDPC encoder for 10GBase-T Ethernet (802.3an), based on Gallager s A algorithm
quaddecoder_verilog_ise11.2_used_09042010
- Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descr ipted in the Constrained file quad.ucf. To use them, y
askcodec
- verilog实现ask编码器,仿真通过-ask encoder verilog implementation, simulation by
interleaver
- 交织编码器的verilog代码实现,此外有testbench和波形。-the verilog code for the interleave encoder, with the testbench code and waveform screen print.
ldpc_encoder_802_3an_latest.tar
- LDPC encoder in verilog
CMI_endecod
- Verilog HDL实现CMI编码和解码,在QuartusII下完成仿真验证。-CMI encoder an decoder using Verilog HDL.
dvb_S_encoder_mb86391
- circuit video encoder mpeg ts for dvb s, base on fujitsu MB86391
bch_encode
- this bch encoder verilog code-this is bch encoder verilog code
mtspeed
- m法t法编码器测速 verilog语言 m法采样时间可调 t法间隔周期可调-m method t method m encoder velocity verilog language law law sampling time interval period adjustable adjustable t
PRIORITY_ENCODER
- A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs. The output of a priority encoder is the binary representation of the ordinal number starting from zero of the most significant input