搜索资源列表
rotary
- 采用verilog语言编写的rotary encoder程序,可以识别出旋转方向。-Rotary encoder verilog language program, you can identify the direction of rotation.
rs_encoder_decoder
- RS编解码源程序,有详细的VERILOG程序,用于纠错-RS encoder and decoder
fVerrilog_Devr
- 朋友,我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的,现在就将她的Verilog源码也一并贡献给大家:8位优先编码器,乘法器,多路选择器,二进制转BBCD码,加法器,减法器,简简单易懂状态机,四位比较器,7段数码管,i2c总线,lcd液晶LCD显示出来,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟 可直接使用。 -Friends, I Jawen. See previous upload a CPLD Development Board VHDL so
my_encode
- 利用verilog语言对一个编码器进行RTL的描述,实现编码器的逻辑功能。-RTL descr iption of an encoder verilog language, the encoder logic functions.
LDPCtest
- ldpc编码器ru算法的verilog语言的完整实现,希望对您有用-ldpc encoder, RU, VERILOG,altera
decoder
- Verilog编写数字编码器,还有激励输入的代码-Verilog prepared encoder, as well as excitation input code
rotary
- Spartan 3E rotary encoder verilog code
H.264_verilog
- 这时H.264编码器的verilog源码,有需要的朋友下载-At this time download the the H.264 encoder Verilog source code, a friend in need
eda-Lab-report
- 三线八线译码器、数据选择器、数据比较器、二进制编码器、译码器的verilog语言输入方法-Three line eight line decoder, data selector, comparator, the binary encoder and decoder of verilog language input method
635026760674375000
- verilog语言编写的一些数字器件.包括译码器,编码器,D触发器等-Verilog language of some digital devices. Including decoder and encoder, D flip-flop, etc
HDB3_
- 利用verilog语言编写的HDB3编码器。-HDB3 encoder using Verilog language.
RS_bmq
- 在QuartusII软件中用Verilog HDL编写的RS编码器的源代码-The RS encoder Verilog HDL prepared with in QuartusII software source code
pri_encoder_using_if
- encoder using if - verilog
RS
- 通过verilog hdl语言实现RS编码器与译码器的设计-Verilog hdl language through the RS encoder and decoder design
encoder104
- 独热码到二进制代码的转换即10输入4输出的二进制编码器的verilog程序。-One-hot code to binary code conversion, or 10 inputs 4 outputs the binary encoder verilog program.
decode38
- 编码器38代码,FPGA实现,语言Verilog编写-Encoder 38 code, FPGA implementation, language Verilog prepared
JPEG
- JPEG Encoder Verilog Source Code
jpeg_encoder
- JPEG 编码器IP核,用verilog语言编写,不支持二级采样。-JPEG Encoder IP Core,The core is written in Verilog and is designed to be portable to any target device. This core does not perform subsampling- the resulting JPEG image will have 4:4:4 subsampling
t2_manchester_coder
- Manchester 编码器的Verilog与VHDL实现,并分别采用moore和mealy机对其进行描述,比较了两种实现方法的不同。并且每种情况都给出了测试脚本,希望对您有用。-Manchester encoder Verilog and VHDL realization and moore and mealy machines were used to describe it, compare the two implementations of different methods. And
conv_encode
- 本设计是一个基于FPGA的咬尾卷积码编码器设计,要求使用verilog语言编写编码器模块,通过编译和综合,并通过matlab和modelsim仿真对比验证设计结果。-The design is an FPGA-based tail-biting convolutional code encoder design requires the use verilog language encoder module, through compilation and synthesis, and by c