搜索资源列表
sinw
- 用verilog写的正弦波发生器，QuartusⅡ环境-Sine wave generator written in Verilog
sin_generate
- verilog 实现 dds正弦 函数信号发生器 verilog 实现 dds正弦 函数信号发生器-verilog achieve dds sine function signal generator verilog verilog dds sine function signal generator the dds sine function signal generator
address_gen
- 基于FPGA使用Verilog语言构成的DDS信号发生器-DDS signal generator based on FPGA using Verilog language constitutes
signal_generator
- 信号发生器 可以通过该程序产生对应的波形 用Verilog语言编写实现 希望能对大家有帮助-The signal generator can generate through the program corresponding to the waveform using the Verilog language
hdl
- Verilog code for the PRBS generator, checker and analyzer.-Verilog code for the PRBS generator, checker and analyzer.
manchester_verilog
- 曼彻斯特码生成器（Verilog源代码）,可以在FPGA上进行验证。-Manchester code generator (Verilog source code), and can be verified on a FPGA.
LSY_wave
- 比赛时写的李萨如波形发生器的代码，用verilog写的，里面集成数据采集和DDS波形发生。-Game when writing the the Lissajous waveform generator code, written in verilog the inside integrated data acquisition and DDS waveform generation.
fashenqi(shunxu)
- Verilog 这个程序是一个关于顺序形成的发生器，希望大家多多批评指正，可用之人能够用得到-Verilog This program is a sequential formation generator, and hope a lot of criticism and the person available to get
Homework4
- 4x4矩阵乘法，使用pipeline结构，可以在AutoESL中综合出Verilog，并在System Generator中测试通过。-Matrix multification in systolic way for AutoESL synthesis
cshiyan2012
- 基于EDA软件平台上，用硬件描述语言verilog设计完成分频器、计数器、串行移位输出器、伪码发生器、QPSK I/Q调制器、QPSK I/Q解调器，基于选项法中频调制器，再将各个模块综合起来组成一个完整系统；并用quartusII软件对其进行仿真验证。-EDA software platform based on the hardware descr iption language verilog design complete shift of the frequency divider,
uart
- 串口通信控制器的Verilog实现。包含4个模块：顶层模块、波特率发生器模块、发送模块和接收模块-The serial communication controller Verilog. Contains four modules: the top-level module, the baud rate generator module, transmitting module and receiver module
liushuideng
- 利用system generator生成的流水灯verilog代码，matlab的model文件也在其中。在spartan3A上验证通过-The verilog code system generator to generate light water Matlab model file also. Spartan3A on validation by
xuliefashengqi
- 序列发生器和检测器的verilog代码编写。-Sequence generator and sequence detector realization with verilog
signal_generator
- 基于FPGA的信号发生器的verilog实现-FPGA-based signal generator verilog implementation
DDS_AD9854_For_FPGA
- DDS_AD9854_for FPGA ,FPGA开发下的verilog源代码，信号发生器-DDS_AD9854_for FPGA, verilog source code, signal generator.
final_sawtooth
- sawtooth generator in verilog
pnsequence.v
- pn sequence generator in verilog
zhengxian
- verilog的正弦函数信号发生器的设计。可生成不同的正弦函数信号波形。-verilog sine function signal generator design. Can generate a different signal waveform of the sine function.
UART-DISPLAY
- lcd 显示，Verilog语言，串口接收数据，并在LCD中显示，波特率9600，包括主文件，LCD控制文件，波特率发生文件-lcd display Verilog language, serial port to receive data, and the LCD display, baud rate of 9600, including the master file, the LCD control file, the baud rate generator file
fpga_Uart
- 串口通信控制器 verilog实现含波特率发生模块，发送、接收模块程序以及xilinx所有工程文件-The serial communication controller verilog containing the baud rate generator module, send, receive module program xilinx all project files