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ca_prng_latest.tar
- Pseudo random noise generator/ implemented in VHDL/Verilog
m_4_generater
- m序列发生器，verilog hdl语言 ，4位-m-sequence generator, verilog hdl language 4
No.2DDS
- 用Verilog HDL实现DDS信号发生器。-DDS signal generator using Verilog HDL.
PWM
- 用Verilog编写的PWM产生器，已经在cyclon DE2板子上测试通过，建议用Quartus 10.1综合。-PWM generator using Verilog.
VeriRISC_CPU_Verilog
- Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clo
5-15
- 用verilog语言实现基于DDS技术的余弦信号发生器，其输出位宽为16比特-Verilog language cosine signal generator based on DDS technology, the output bit width is 16 bits
5-17
- 用verilog实现一个基于流水线结构的正、余弦信号发生器-Based on Pipeline Structure verilog to achieve a sine and cosine signal generator
cmi
- 运用4阶m序列产生信号源 即消息码 用verilog编程实现cmi的产生-The use of fourth-order m-sequence generator source message code Verilog programming cmi generation
parity
- Eight bit Parity generator in verilog with Mux Generador de paridad de ocho bits con multiplexor
DDS
- 用verilog语言实现，DDS信号发生与嵌入式逻辑分析仪的调用，程序功能完整 -Using verilog language, DDS signal generator with embedded logic analyzer called, the program features a complete
DCM
- CCD SENSOR 驱动信号发生器，基于VERILOG HDL-CCD SENSOR driving signal generator, based on VERILOG HDL
10010sequece-detector
- 序列发生器，Verilog HDL语言描述，包含文件说明和波形截图-Sequence generator, Verilog HDL language descr iption , contains the file descr iption and waveform capture
M=15generator
- 模15序列发生器，Verilog HDL语言描述，包含文件说明和波形截图-mod15 generator, Verilog HDL language descr iption , contains the file descr iption and waveform capture
zhengxianbo
- 正弦波发生器，基于verilog语言编写的，不用用DAC模块，直接输出0和1电频，经过RC滤波后就可得到波形-Sine wave generator, based on verilog language, do not use the DAC module, direct output power frequency 0 and 1, RC-filtered waveform obtained after
clock_generator
- 802.11a时钟产生、分频模块，verilog源码-802.11a clock generator, frequency module, verilog source
m_xulie
- 在quaritusII的开发环境下，verilog语言编写的m序列发生器代码，这种算法简短而有效，非常实用。-In quaritusII development environment, verilog language of m sequence generator code, this algorithm brief but effective, very practical.
DDS_signal_genarator
- 这是一个利用verilog语言编写的信号发生器的例子，值得参考-this is a code about signal generator by VIERILOG LANGUAGE!
lutsr
- verilog design of lut sr random number generator
wave_freq
- 在VHDL/verilog环境下产生可调频率的波形，如三角波，方波，矩形波，同时支持计数功能，供参考-Adjustable frequency waveform generator in VHDL/verilog environment, such as triangle wave, square wave, rectangular wave, while supporting the counting function, for reference
crc-16b-parallel
- CRC generator in verilog hdl