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VBuffer_1c6
- 视频采集并锁存到SDRAM中的完整代码,运行环境为QII,VHDL与标准参数宏模块调用混合设计 是学习视频采集的很好的参考-Video Capture SDRAM and latches to the integrity code, the operating environment for QII. VHDL standard parameter-called hybrid module is designed to study the Video Capture good reference
lc2
- this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 mode
S8_VGA.VGA显示接口的verilog控制程序
- VGA显示接口的verilog控制程序。用于VGA显示器的控制驱动,VGA display interface Verilog control procedures. Control for VGA display driver
hardh264
- 一个硬件H264编码的VHDL源码,用于FPGA开发,适合IP摄像头等视频设备输出数据的编码。用Xilinx工具测试过,但代码不只是用于Xilinx。-A hardware h264 video encoder written in VHDL suited to IP cameras and megapixel cameras. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools
shipintuxiang
- 基于VHDL,实现视频图像的行列计数器,已经调试仿真通过可用.-Based on VHDL, the ranks of video image counter, has been simulated through the available debugging.
PAL
- PAL_D电视信号VHDL以及verilog源程序! FPGA设计PAL_D电视信号!VHDL源程序!两个程序都是黑白的video信号,输出可以直接在视频显示器上显示。 -PAL_D TV signal VHDL and Verilog source!
2
- vhdl的源文件调试 !!!!!!!! flv视频-VHDL source file debugging! ! ! ! ! ! ! ! flv video
5
- vhdl的仿真 quartus 2的flv视频 -VHDL simulation of the flv video quartus 2
vgaoutfiles
- vhdl code for obtaining video output through vga port
MQdecoder
- Verilog HDL 实现的JPEG200的MQ解码-JPEG2000 MQ DECODER BASED ON FPGA, Verilog HDL
my_audio
- 很详细的关于FPGA视频方面的VHDL程序-Very detailed video on the FPGA area VHDL program ..
MAIN_TX_V10
- 8路视频光端机的VHDL源码,此硬件使用以太网的SERDES 借用TBI接口传输PCM视频信号。-8-channel video PDH in VHDL source code
F7-2VT-1DR
- 2路视频光端机的,VHDL源码,使用全FPGA芯片的硬件,内建成帧、时钟、SERDES-2-way video PDH' s, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
xzgl
- 学籍管理系统,学籍 管理系统 Visual C++ Visual Basic DOS Unix_Linux C++ Builder Java Windows_Unix Delphi C-C++ PHP-PERL PHP Perl Python HTML Asm Pascal Borland C++ Others MultiPlatform C++ VFP SQL PDF TEXT WORD VBscr ipt Javascr ipt ASP CSharp CHM FlashMX matlab P
cr_counter
- 视频图像的行列计数器基于VHDL的实现,已经调试仿真通过-Video images VHDL-based implementation of the ranks of the counter has been adopted debugging emulator
VGACTL
- VGA VHDL VIDEO CONTROLLER
tron
- Tron game, a video game developed by VHDL.
fj
- 从视频信号中分离出场同步、行同步、场消隐、行消隐等同步信号,用VHDL实现。-Separated from the video signal played simultaneously, line synchronization, field blanking, line blanking and other synchronous signals, using VHDL implementation.
Form1
- “文字格式”工具栏 “文字格式”工具栏- Visual Basic(7880) Visual C++(306) VBscr ipt(76) Others(73) WINDOWS(55) VBA(48) C-C++(42) MultiPlatform(39) ASP(38) Delphi(34) Java(30) CSharp(29) SQL(22) C++ Builder(22) Windows_Unix(20) CHM(16) WORD(14) C++(14) DOS(13) PDF(11
pid-fpga-vhdl-master
- 6. Show how accurate your predicted model is, also explain in what situation and why it does (not) perform that well (in report and video). 7. If you re-train the network for your own custom images, you can choose different training options. Explain