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- adder verilog. is not c language. just an adder in verilog
Four-adder-and-four--counter
- 4位全加器和计数器的verilog的例程,还有四位全加器的仿真程序。-Four QuanJia device and counter verilog of the routines, and four QuanJia device simulation program.
Fast-adder-design-using-verilog
- 用Verilog设计各种快速加法器(四位先行进位加法器、选择进位加法器、流水线加法器)-Verilog design all kinds of fast adder (four first adder, select adder pipelined adder)
CarryLookaheadAdder64
- 一个64位超前进位加法器,verilog语言描述。-A 64 bits carry look ahead adder, verilog
acc
- 全加器,比较器等verilog hdl代码 以及测试代码-Full adder verilog hdl code of the comparator
Verilog-examples
- verilog 例程,白金手册,很多实用例程,加法器,循环编码器-verilog routines, platinum manual, many utility routines, adder, cycle coding and more
adder
- This the program for addition in verilog-This is the program for addition in verilog
adder
- 可加可减器,使用verilog编写,4位加减器。-Can be increased or decreased, verilog prepared 4 addition and subtraction.
adder
- adder in verilog only with combinational logic use
full_a4
- 4位全加器的verilog程序设计-Four full adder verilog programming ...
ripple_carry_adder
- 行波加法器,Verilog语言编写。行波加法器,Verilog语言编写-The line wave adder Verilog language. The line wave adder Verilog language
add
- 用verilog实现加法器程序,通过仿真验证-Adder verilog achieve program is verified by simulation
float
- 32位浮点加法器 verilog语言编写-32-bit floating-point adder verilog language
add
- 加法器的verilog代码希望对需要的人起一定的参考-Adder verilog code hope for those who need to play a certain reference
code
- 32bits流水线加法器,verilog语言的,xilinx公司芯片上运行通过-The 32bits pipelined adder verilog language, xilinx chip run through
daima
- 32bits进位选择加法器,verilog语言的,xilinx公司芯片上运行通过-The 32bits carry select adder verilog language, xilinx chip run through
daima
- 32bits提前进位加法器,verilog语言的,xilinx公司芯片上运行通过-The 32bits advance carry adder verilog language, xilinx chip run through
code
- 32bits补码加法器,verilog语言的,xilinx公司芯片上运行通过-The 32bits complement adder verilog language, xilinx chip run through
4bit-parallel-adder
- The program contains verilog code for 4bit parallel adder
Carry_Select_Adder_Verilog
- 进位选择加法器,verilog实现。包含3个TB。-Carry Select Adder. Verilog fulfilled. Three testbenches included.