搜索资源列表
4bitadderkoggestone
- Kogge stone adder implementation in verilog
Task1_WithCLK
- half adder with verilog coding for
Task1
- verilog code for a full adder
lab1
- 用半加器搭建全加器 使用Verilog语言(Using a half adder to build a full adder, using the Verilog language)
ModelSim
- Implementing a full adder in ModelSim by using Verilog Language
add
- 一个用quartus原理图输入的全加器,(A full adder with quartus schematic input,)
CLA代码
- 计数器跳跃进位加法器CLA代码,加法器计数器(adder with four 8-bit groups. 8-bit adder will have two 4-bit groups.)
4Bit超前进位加法器门级电路设计与仿真
- 用门级网表的方法对4Bit超前进位加法器门级电路连接关系用verilog语言进行描述(The connection relation of the gate level circuit of 4Bit carry adder is described in Verilog language with the method of gate level netlist)
code
- adder 18b trong chuong trinh verilog
adder_4bits
- 实现四位先行加法器的功能以及测试代码,其中adder_4bits.v为模块代码,adder_4bits—_tb.v为测试代码。还附加 部分其他加法器测试代码(Implement the function of four bit first adder and test code)
gray_counter
- 格雷码计数器实质包含了三个部分 格雷码转二进制、加法器、二进制转格雷码。通过quartus II 自带的Modlesim仿真验证了 能够实现二进制和格雷码之间的转换(Gray counter essence contains three parts, gray code to binary adder, binary gray code conversion. Modlesim simulation by quartus with II verified to achieve the conve
float_adder
- 实现可调维度的浮点数加法运算,内涵各个子模块和testbench(Able to achieve the float numbers adding operation.)
CSA.tar
- A Carry Select Adder.
RCA.tar
- A ripple carry adder.
csa_codes
- carry_select_adder for 16-bit in verilog
module demultiplexer1
- Verilog code for demultiplexer
mux_with multiplier
- mux to use with adder with full adder and half adder
add.v
- 这是verilog的加法器。它可用于超大规模集成电路设计。(This is an adder by Verilog. It can be used for VLSI design.)
Verilog_m_lx
- 一个简单的verilog小程序,适合初学者学习(A simple Verilog small program, suitable for beginners to learn)
FP_adder
- 32 bit floating point adder with testbench