搜索资源列表
The-Duck
- Crack for Quartus II 8.0
NiosII_Software_Developer_Handbook
- Nios II Software Developer s Handbook Nios II软件部分开发手册 也可以到Altera官方网上下载-Nios II Software Developer s Handbook
FPGA_SOPC_starter
- 很详细的入门文章 对于初学者是不错的参考 也可以下载altera handbook 同样有更经典的案例FPGA_SOPC_starter-FPGA_SOPC_starter
nios2_hardware_tutorial
- NiosII硬件开发指南，同样可以到Altera官方网站下载最新版的turorial nios2_hardware_tutorial-nios2_hardware_tutorial
embedded_design_handbook
- embedded_design_handbook Altera NiosII嵌入式系统SOPC开发handbook-embedded_design_handbook
hello_flash
- hello_flash是ALTERA的NIOSII核的标准程序。读写FPGA外带的Flash。-ALTERA the hello_flash is standard procedure for nuclear NIOSII. Hit-and-run of the FPGA to read and write Flash.
Altera_hello_led
- hello_flash是ALTERA的NIOSII核的标准程序。读写FPGA外带的Flash。-ALTERA the hello_flash is standard procedure for nuclear NIOSII. Hit-and-run of the FPGA to read and write Flash.
AlteraFPGA_hello_led
- Altera的FPGA的经典程序，非常样板化的。初学者好好学学。-Altera' s FPGA classic procedures, very model of the. Good for beginners to learn.
crack_qii90
- altera quartus 9 crack working
ddsdds
- 摘 要：介绍了直接数字频率合成 (DDS) 技术的基本原理，给出了基于Altera公司FPGA器件的一个三相正弦信号发生器的设计方案，同时给出了其软件程序和仿真结果。仿真结果表明：该方法生成的三相正弦信号具有对称性好、波形失真小、频率精度高等优点，且输出频率可调。关键词：直接数字频率合成；现场可编程门阵列；FPGA；三相正弦信号 (2009-01-04, VHDL, 99KB, 9次) -hgfhtht rrgtsrt rthg rgrswt sgethwrathwtHY TSRTTHSRH
lpm_ram
- 一个基于quartus的LPM_RAM例子，VHDL语言写的，通过仿真测试-Quartus the LPM_RAM based on examples, VHDL language, and through simulation testing
DE2_Demonstrations
- altera DE2开发板相关应用资源，里面包含许多相关的模块的现成vhdl程序-DE2_Demonstrations of altera
an497_design_example_altera_CPLD_LCD
- altera cpld lcd controller
ALTERA_FPGA_PCB
- 这是5个基于altera的fpga的PCB板电路图，对于fpga PCB设计是很有用的-This is based on five of the fpga the altera circuit board PCB, the fpga PCB design is very useful
keyboard
- 44键盘按键循环显示（用VHDL硬件描述语言通过Altera软件实现）-44 keyboard keys cycle display (using VHDL hardware descr iption language software through Altera)
DDS
- DDS频率合成器（使用VHDL硬件描述语言，通过Altera QuartusII开发）-DDS frequency synthesizer (using VHDL hardware descr iption language, through the development of Altera QuartusII)
VGA_640480VGA
- 640480VGA 控制器 （使用VHDL硬件描述语言，通过Altera QuartusII 开发）-640480VGA controller (using VHDL hardware descr iption language, through the development of Altera QuartusII)
USB
- USB的VHDL实现源码（使用VHDL硬件描述语言，通过Altera QuartusII 开发）-USB to achieve the VHDL source code (using VHDL hardware descr iption language, through the development of Altera QuartusII)
fast_pll
- fpga的pll锁相设计，altera器件EP1s25的选用、设计-phase-locked pll of fpga design, altera devices EP1s25 selection, design
pfl_d
- fpga的pll锁相设计，altera器件EP1s25的选用、设计-phase-locked pll of fpga design, altera devices EP1s25 selection, design