搜索资源列表
bcd
- Generic binary BCH encoding decoding library for Linux v2.13.6.
Calculator
- VHDL计算器，涉及PS2输入，VGA视频输出，加法器，BCD转化。可以通过研究代码学习以上知识-VHDL calculator, involving PS2 input, VGA video output, the adder, BCD transformation. You can learn more knowledge through research code
LED_BCD8x7seg
- bcd 8*7 seg led display code in assembly level coding
8052-Basic
- 这是一个完整；BCD浮点包为8051微— 控制器。它提供了8位的指数，精度 ；范围从127到127。尾数是压缩BCD码，而 ；指数是伪二表达的补充。一零指数 ；是用来表示数为零。指数值为80H或 ；大于意味着指数为正，即80h = 0， ；81h = E + 1，82H = E + 2等。如果指数7FH或更少， ；指数为负，7FH＝1，7eh = E-2，等等。 ；所有的数字都被假定为归一化和所有的结果 归一化后的计算。归一化的尾数＞＝10。 ；<
excer
- bcd counter code with pdf file for help and better understanding
second
- 利用Verilog HDL语言进行数字系统设计实现秒表的设计，涵盖原理图设计、文本设计以及进行波形仿真，并有对应的报告。报告中还包括BCD/7段译码集成电路74LS47仿真实验、单管分压式稳定工作点偏置电路仿真实验和8路智力竞赛抢答器电路设计-Use Verilog HDL language design and implementation of digital systems design stopwatch, covering schematic design, text, design,
translate
- 利用程序在ROM中设置40个固定数值在41～80的BCD码数据，程序运行时，把该数据块读到片内RAM的20H～47H区间，然后把该数据块变换为BIN码（二进制制）存于片内的48H ～6FH区间，再把BIN数据变换为ASCII码存于片外RAM 0100H ～ 013FH区间-The use of the program set in the ROM 40 is fixed at the value 41 ~ 80 BCD code data, the program runs, to read t
bcd2ftsegdec
- FPGA bcd 7 segments display example
dance-box
- 利用FPGA实现的跳舞机，有VGA的模块，二进制到BCD转换的模块等-Using FPGA to achieve Dance Dance Revolution, have VGA module binary to BCD conversion modules, etc.
jsq
- 基于FPGA的计算器，可以实现加减乘除运算功能，由于时间问题，浮点运算未能实现，其中的二进制与BCD码相互转换的模块可以使用-FPGA-based calculator, arithmetic calculation function can be achieved, due to time issues, floating-point operations failed to achieve, including binary and BCD code conversion modules t
bcdflag
- verilog code bcd adder using flag register
bcd27seg
- Tranfer BCD to 7 Segs
EDA-miaobiao
- EDA课程设计，作为秒计数器的系统时钟512Hz，秒表计数为两位BCD计数，具有减计数和加计数功能-EDA curriculum design, as the seconds counter system clock 512Hz, stopwatch count as two BCD counting, counting and processing has reduced counting function
MCS51
- 二进制定点数运算/二进制浮点数运算/十进制（BCD码）数运算/代码转换/数据变换/排序、查找和非线性算法/数学函数/树和图/ 延时与跳转控制/人机交互接口/单片机测控接口/51单片机内部资源编程实例/单片机数据传输接口/波形发生与控制实例/C51单片机软件抗干扰和数字滤波-Binary fixed-point number operations/binary floating-point operations/decimal (BCD) operation/sorting/code conver
Decodificador
- decodificador bcd 7 segmentos vhdl
3Digit_7segment_ind_decoder
- 3 Digit BCD to 7 segment indicator decoder
MATLAB-and-Verilog-codes
- there are 5 files. the first two codes are written in Matlab as m-files in control system design to show step responses. in contrast, the final three codes are written in verilog ( Quartus II) used in Altera one of them for BCD adder and the other fo
BCD_7SegFPGA
- Implement a generic converter BCD to Display 7 segment in a FPGA
binstr
- Descr iption: Converts a 64-bit binary integer to bcd.
b_to_bcd
- 8位的二进制码转bcd码，可以在数码管上直接显示数字。-BCD to 8-bit binary code, can directly on the digital tube display digital.