搜索资源列表
CAN_IP.rar
- 这是CAN总线控制器的IP核,源码是由Verilog HDL编写的。其硬件结构与SJA1000类似,满足CAN2.0B协议。,This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
ADC0832_test.rar
- ADC0832是一个8-bit的ADC转化芯片,工作频率为250Khz,最大频率可达400Khz,转化通道有两个,输入电压可分有单端或差分形式。本测试使用单端电压输入形式,从昔年的CH0输入电压,使用Xilinx XC3S200AN开发板,并且使用Xilinx ise工具中的ChipScope工具来查看转化后的DO数据是否正确。经验证,输入电压范围是0V--5.5V,当电压达到5.5V时,满刻度.,ADC0832 is an 8-bit conversion of the ADC chip, t
i2c_ip.zip
- I2C的ip核,Verilog实现,可以直接用在你的项目中。I2C是一种简单实用的通讯协议。,I2C' s ip nuclear, Verilog realization, you can directly use in your projects. I2C is a simple and practical protocol.
Verilog_VGA.rar
- 程序实现的功能是在VGA显示器上显示彩色条纹,共8种颜色,可以使用嵌入式逻辑分析仪观测信号。,Procedures for the realization of the function is displayed on the monitor in the VGA color stripes, a total of eight kinds of colors, you can use the embedded logic analyzer signal observation.
DW8051.rar
- Synopsys 公司的DW8051源代码,用verilog编写的,代码很完整,可以仿真,对采用8051核做嵌入式的人很有帮助,Synopsys company DW8051 source code, written with Verilog, the code is complete, can be simulated using 8051 nuclear helpful people who do Embedded
ddc.rar
- 数字下变频器的matlab实现,一定的设计指标,可以用来知道vhdl程序设计,Digital Down Converter for matlab realized, certain design specifications that can be used to know VHDL Programming
adc0804_new.rar
- AD0804驱动,使用新的查表方式,可大大的降低数值运算,节省CPLD的资源,AD0804 driver,using a new method_look up table,which can save a lot of resources of CPLD
fifo_32_4321.rar
- 用verilog写的输出数据宽度可变的FIFO,输入数据为32-bit,输出数据可以配置为4-1任意bit。有设计文件和testbench,Use verilog to write a variable width of the output data FIFO, input data for the 32-bit, output data can be configured as 4-1 arbitrary bit. There are design files and testbench
MIPS
- 组成原理大作业--基于MIPS的运算器设计,内附详细设计文档,包含设计文档和使用手册,主程序,测试程序,还有设计的框图等。实现了可以执行基本的MIPS有关运算器相关的指令共17条,用Verilog编写。-Composition Principle big operation- based on the MIPS computing design, containing a detailed design document, including design documentation and u
canbus
- CAN总线的FPGA实现,用Verilog编写,代码完整,而且有很完善的测试代码,用ISE直接打开,学习FPGA进阶的好项目-CAN Bus FPGA, written with Verilog, code integrity, but also very good test code, using ISE directly open, a good project to learn advanced FPGA
fir_lms
- 一个不错的关于lms算法的verilog代码,算然只有两级,但是对了解lms用HDL描述有很好的理解作用。希望对大家有用~-A good lms algorithm on the verilog code, development environment, I can not find, even if the vhdl it! We hope to be useful
8051IP_Verilog
- 8051核,verilog实现。可以直接用在FPGA中,在此基础上可以和用真正的8051一样的进行单片机的学习。-8051 Nuclear, verilog achieve. Can be directly used in the FPGA, in this basis can be used as the real conduct of the 8051 single-chip learning.
DDR3
- DDR3控制器,基于Altera平台,修改管教后直接可以下载进PFGA-DDR3 controller, based on Altera platform, modify the discipline can be downloaded directly into the PFGA
rs232
- 完整的RS232 Verilog源代码,支持波特率可调,支持调试命令,配合串口调试工具,可作为FPGA开发中的调试平台。-Full RS232 Verilog source code, support for baud rate is adjustable to support debugging command, with the serial debugging tools can be used as the debugging FPGA development platform.
ssram
- 同步静态RAM读写程序,可用作模块,已通过ISE12.4验证-Synchronous Static RAM read and write procedures, can be used as modules, have been verified by ISE12.4
speech
- 用verilog HDL实现自相关算法! RTL级可综合代码! 通过modelsim5.6仿真和quartusii7.1综合!-Verilog HDL using auto-correlation algorithm to achieve! RTL-level code can be integrated! Through simulation and modelsim5.6 integrated quartusii7.1!
TS_Process_V1.0
- DVB 加扰软件,对TS流文件进行加扰,符合DVB标准-it s a dvb scramble software . it can scrambling ts stream file ,which apply for dvb standards
PWM256
- Verilog 所寫的可程式 PWM 信號產生器. 特點是設定參數時不會產生Glitch現象. 包含二個 .do 檔給 model*sim 幫助編譯及模擬.-A PWM generator writing in Verilog. This module will generate glitch while changing the setting. Including 2 .do files which can help compiling and simulating in the model
altera_fft
- alter官方fft程序 使用verilog编写 需要的同学可以下载-alter the official fft program uses verilog prepared students in need can be downloaded
mouse
- 基于PS/2协议的鼠标驱动程序,用Verilog语言写成,可以用于任何型号的FPGA的驱动。-Based on PS/2 protocol mouse driver written using Verilog language can be used for any type of FPGA-driven.