搜索资源列表
canbus(FPGA)
- 基于FPGA的can 总线设计，采用verilog语言编写。在FPGA的开发环境下，新建一个工程，然后将本文件中的各个源代码添加进工程里，即可运行仿真。-FPGA-based bus design can use verilog language. FPGA development environment, a new project, and then the paper all the source code to add the project, Simulation can be run
canbus开发
- can 总线开发源码，可参考
canbus
- 实现CAN总线的通信，并通过测试验证，用verilog在FPGA上实现-CAN bus communication, and tested to verify that, in the FPGA using verilog
canbus
- CAN总线的FPGA实现，用Verilog编写，代码完整，而且有很完善的测试代码，用ISE直接打开，学习FPGA进阶的好项目-CAN Bus FPGA, written with Verilog, code integrity, but also very good test code, using ISE directly open, a good project to learn advanced FPGA
canbus
- verilog 和VHDL实现的can总线接口代码-the realization of verilog and VHDL code of the can bus interface
canbus
- canbus verilog实现，原代码文件-canbus verilog implementation, the original source document
canbus
- 用verilog编写实现的CAN总线控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the verilog source code to achieve the CAN bus controller, bring their own testbench, after decompression project file can be opened with the ISE.
canbus
- CAN总线的FPGA实现源代码,Verilog语言实现-CAN Bus FPGA source code
canbus
- 此例参照SJA1000CAN通信控制器，通过CAN总线控制器完成CAN总线的通信协议。所传文件为CAN总线的VERILOG代码。-This reference SJA1000CAN communication controller, to complete the communication protocol of CAN bus through the CAN bus controller. The transfer document for the CAN bus VERILOG code.
CANBUS
- 本文包含了CAN的verilog程序及测代码-This article contains the CAN verilog code and testing procedures