搜索资源列表
complex
- 时钟，信号灯verilog for FPGA
32_bit_complex_multiplier
- 一款32位复数乘法器，用verilog写的。-32_bit complex multiplier,written in verilog HDL.
verilog-program
- 国外经典verilog程序集锦，含有从最简单的定时器创建到复杂逻辑的实现。-Classic Collection verilog program abroad, with the timer created from the most simple to complex logic.
cmultip
- 用VERILOG HDL 实现节省乘法器的16位复数乘法器-With VERILOG HDL achieve savings of 16-bit complex multiplier multiplier
DSP
- 从算法设计到硬线逻辑的实现：复杂数字逻辑系统的Verilog HDL设计技术和方法，结合DSP算法介绍verilog HdL 设计。-From algorithm design to achieve hard-wired logic: complex digital logic system Verilog HDL design techniques and methods, combined with DSP algorithm design verilog HdL introduced.
FPGA_jiaocheng_yu_shiyan
- 最重要的是七个从简单到复杂的实验，包括：基础实验一_FPGA_LED 基础实验二_seg7实验以及仿真 基础实验三_SOPC_LED 基础实验四_Flash烧写 基础实验五_定时器实验 基础实验六_按键以及PIO口中断实验 实验七_网卡使用 ，这些实验室用到了SOPC BUILDER 与NOIS ii ,使用Verilog 编写，有实验板和没有实验板的都可以用来学习。 其次还包括： FPGA开发板各存储器之间的联系、 多处理器文档 、 USB_UART等文档，很好用的文档，您下了相信不会后悔！-
128323996741562500
- 数字电路设计与verilog编程实现，主要实现专用复杂的电路系统。-Digital Circuit Design and Verilog programming, mainly dedicated to achieve complex circuit system.
FastCplxMuply
- This zip folder contains the verilog code for fast complex multiplication source code and its test bench
Verilog
- 通过本文章的学习能够使我们设计一些简单的逻辑电路和系统。很快我们就能过渡到设计相当复杂的数字逻辑系统。-To learn through this article, will enable us to design some simple logic circuits and systems. Soon we will be able to transition to the design of complex digital logic systems.
myinterpolation
- 复杂的插值函数，用于颜色空间转换 verilog-The complex interpolation function for color space conversion verilog
135classic_example_of_Verilog_design
- Verilog的135个经典设计实例，由简到繁，由浅入深，值得收藏！-Verilog' s 135 classic design example, from simple to complex, Deep and worth collecting!
31705301sdram-control-verilog
- Summary: InterPreTS (Interaction Prediction through Tertiary Structure) is a web-based version of our method for predicting protein-protein interactions (Aloy and Russell, 2002, Proc. Natl Acad. Sci. USA, 99, 5896-5901). Given a pair of query sequenc
83399055ref-sdr-sdram-verilog
- Summary: InterPreTS (Interaction Prediction through Tertiary Structure) is a web-based version of our hod for predicting protein-protein interactions (Aloy and Russell, 2002, Proc. Natl Acad. Sci. USA, 99, 5896-5901). Given a pair of query sequences,
Verilog
- 针对Verilog语言，提供了135个经典的示例程序代码，从简单到复杂，一步步的深入。-For the Verilog language, providing 135 classic example code, from simple to complex, step by step in depth.
Verilog-HDL-design
- verilog方法逻辑设计教程，教会复杂电路设计的基本-verilog tutorial method of logic design, circuit design of the basic church complex
verilog
- 一些常用verilog代码实例，包含组合逻辑电路，时序逻辑电路，和一些复杂电路模块-Some commonly used verilog code examples.Contains the assembly logic circuit, temporal logic circuit, and some complex circuit module
Verilog-Design
- 复杂数字电路逻辑设计与实现，主要涉及算法的实现和具体的应用，很适合初学者入门-Logic design and implementation of complex digital circuits, mainly related to the implementation of the algorithm and the specific application, it is suitable for the beginner
complex-mul
- complex multiplier in verilog code is uploaded
夏老师讲义保存
- 书中的内容从算法和计算的基本概念出发，讲述如何由硬件逻辑电路来实现复杂数字逻辑的方法和技术。(The content of the book is based on the basic concepts of algorithms and computing, and describes how to implement complex digital logic by hardware logic circuits.)
16_COMLEX ADDER
- Complex Numbers are denoted in the form a+ib where a is the real part and b is the imaginary part