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实现卷积编码和相应的维特比译码(卷积码编码器为(2,1,3),维特比译码针对第1、3位模二加和第1、2位模二加)-Convolutional coding and the corresponding realization of Viterbi decoding (convolutional code encoder for the (2,1,3), Viterbi decoder bit mode for the first 1,3 and 1,2 position two plus two
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这是一套完整的支持wimax 16e协议CTC的编译码程序,
主程序在demo.c
译码器:tcdecoder.c
编码器:tcencoder.c-/* This program simulates the classical turbo encoding-decoding system on PC.*/
/* It uses parallel concatenated convolutional codes described in Figure 2.9 in Chapter
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卷积码编码器的实现,用的是vhdl语言。这是毕设时做的,已经调通。-Convolutional code encoder implementation, using vhdl language. This is done when the complete set has been transferred through.
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用于生成信道编码算法仿真当中所使用的编码器输入信息,适用于分组码、卷积码和tubor码等。-Channel coding algorithm used to generate simulations were used in the encoder input for block codes, convolutional codes and tubor codes.
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在编码器复杂度相同的情况下,卷积码的性能优于分组码,因此卷积码几乎被应用在所有无线通信的标准之中,如GSM, IS95和CDMA 2000 的标准中。-Complexity in the encoder the same circumstances, convolutional codes perform better than block codes, the convolutional code is used in almost all wireless communication sta
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卷积码编解码,卷积码是一种性能优越的信道编码,它的编码器和解码器都比较易于实现-Convolutional encoding and decoding, convolutional code is a superior performance of channel coding, it' s the encoder and decoder are relatively easy to implement
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卷积码编码与解码技术,Viterbi译码算法,广泛的应用于现代通信中它的编码器和解码器都比较易于实现-Convolutional encoding and decoding technology, Viterbi decoding algorithm, widely used in modern communications it encoder and decoder are relatively easy to implement
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convolutional code is a kind of code memory, in any given unit of time, the encoder output n this time not only with the elements of the k input, but also with the input m. Convolutional codes are usually stated as : (n, k, m)
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卷积码的C语言代码实现,其中包括(2,1,2)卷积码编码器和维特比译码的实现。-Convolutional code C code implementation, including the (2,1,2) convolutional code encoder and Viterbi decoding.
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Viterbi encoder/decoder for convolutional codes
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卷积码的编码器是由一个有k个输入端、n个输出端、m节移位寄存器所构成的有限状态的有记忆系统,通常称它为时序网络。-A convolutional code encoder is composed of a k-th input terminal of the n output terminals, m section shift register constituted by a finite state memory system, the usually call timing networ
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CDMA中的turbo码仿真,tuebo编码器的仿真 很不错!-This scr ipt simulates the classical turbo encoding-decoding system.
It simulates parallel concatenated convolutional codes.
Two component rate 1/2 RSC (Recursive Systematic Convolutional) component encoders
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1/2,3/4可配置的卷积码编码,其中需要用要FIFO的IP核-1/2, 3/4 convolutional code encoder can be configured with a FIFO wherein IP core
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用于卷积码编码,实现输入二进制数据流进行编码-For the convolutional code encoder, the input binary data stream to be encoded
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The encoder and decoder of convolutional code
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主要是Turbo码的编码和译码,可以选择信噪比、 译码算法 还有图显示 可以直接使用 代码没有问题-This scr ipt simulates the classical turbo encoding-decoding system.It simulates parallel concatenated convolutional codes.Two component rate 1/2 RSC (Recursive Systematic Convolutional) component enc
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The source code simulating the encoder and decoder of a rate 1/2 systematic convolutional code using the Maximum Likelihood Viterbi algorithm.
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本设计是一个基于FPGA的咬尾卷积码编码器设计,要求使用verilog语言编写编码器模块,通过编译和综合,并通过matlab和modelsim仿真对比验证设计结果。-The design is an FPGA-based tail-biting convolutional code encoder design requires the use verilog language encoder module, through compilation and synthesis, and by c
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(2,1,7)卷积码编码器
能设置初始状态和生成多项式的系数-(2,1,7) convolutional code encoder can set the initial state and the generator polynomial coefficients
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TD-LTE中(3.1.7)咬尾卷积码编码器verilog代码-Tail-biting convolutional code encoder verilog code
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