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40caiji
- 本源码是基于CPLD的40路数字信号采集采集一组数据提交单片机处理并受单片机控制-The source is based on the CPLD 40 road Digital Signal Acquisition Acquisition submit one set of data and is subject to deal with single-chip single-chip control
quartus-train
- 这是一款CPLD的在线调试软件。能够满足用于学习者的一般要求。-This is a debugging software online CPLD. Be able to meet the general requirements for learners.
jishuqi
- CPLD器件中常用编程，对于多进程做了很好的处理，能实现0到59计数，还可自己根据需要调整，实现多种计数功能，从而实现时分秒计时器的功能-CPLD devices commonly used in programming, for many the process to do a very good deal, can achieve 0-59 count, but also need to be adjusted in accordance with their own, achieve a
example10
- ：正弦波发生器例程，包括了直接数字频率合成(DDS)的原理以及如何应用CPLD产生频率可控频率的正弦信号。-: Sine wave generator routine, including a direct digital synthesizer (DDS), as well as the application of the principle of frequency control CPLD generated sinusoidal signal frequency.
MAX7128
- 关于epm7128的一些资料，常用的cpld开发新片，也是学习cpld 的首选-good
cam3
- 使用CPLD控制摄像头的电子快门。控制范围连续可调1us到20ms。-using CPLD to controll camera s shutter speed
bym
- 在Max+plusΠ环境下用VHDL语言编写实现基于CPLD的CMI编译码器设计-In Max+ plusΠ environment using VHDL language CPLD-based design of CMI codecs
ISE7.1i_course
- ISE7.1i 中文教程 适合xilinx的FPGA/CPLD用户-Chinese ISE7.1i the xilinx tutorial for FPGA/CPLD users
MAXII
- 功耗是前一代CPLD系列的十分之一――MAX II器件的动态功耗很低，所以运行功耗较低。MAX II系列功耗是低成本MAX 3000A系列的十分之一。-Power generation CPLD family of the former one-tenth- MAX II device' s dynamic power consumption is very low, so low-power operation. MAX II family of low-cost, power cons
epm1270iopin
- 功耗是前一代CPLD系列的十分之一――MAX II器件的动态功耗很低，所以运行功耗较低。MAX II系列功耗是低成本MAX 3000A系列的十分之一。-Power generation CPLD family of the former one-tenth- MAX II device' s dynamic power consumption is very low, so low-power operation. MAX II family of low-cost, power cons
3serialportcommunicationsource
- 3串行口通讯源码，主要应用与DSP与CPLD，上位机等通讯交互-3 serial port communication source, the main application and DSP and CPLD, interactive communications, such as PC
CCD
- 本程序通过CPLD不同的波形来控制CCD的驱动-This procedure of the waveform through the CPLD to control the different CCD driver
DECODER
- decoder3_8实现了FPGA或CPLD 实现3-8译码器的功能-decoder3_8 to achieve the realization of the FPGA or CPLD decoder functions 3-8
CPLD_Implementation_of_a_Lucky_Dip_Machine
- 摸奖桶程序设计 也就是乐透彩票模拟程序 程序为verilogHDL描述 详细请看英文描述-Digital Electronic Design Automation Workshop on Rapid Prototyping using a CPLD Lucky Dip Machine using the Digilent X-Board
Multi_Debug_Card
- 利用Xilinx XC2C128（Xilinx CPLD）制做的台式电脑的Debug卡及原理图，对于不开机的主板，能侦测出CPU到北桥之间具体那根信号线空焊，用于快速维修不开机之主板。-The use of Xilinx XC2C128 (Xilinx CPLD) desktop computer system to do the Debug Card and schematic diagram for the motherboard does not boot, can detect the
VHDL_Hardware_Language
- vhdl硬件描述语言，对于进行FPGA、CPLD开发的人来说比较有用。-vhdl hardware descr iption language is fundamental to the FPGA, CPLD development of more useful people.
first
- verilog 初学者原代码，万事开头难，ＣＰＬＤ也如此，第一个成功的代码测试往往后续学习的信心。需要的朋友请进-beginners verilog source code, everything is hard in the beginning, CPLD is also the case, the first successful test of the code is often the confidence of the follow-up study. Come friend in n
Key
- key code,for thinx cpld
lcd_palace
- lcd_palace code,for thinx cpld
Sevencode
- Seven code code,for thinx cpld