搜索资源列表
sdram_mdl
- verilog编写的对SDRAM的控制的源代码，开发FPGA/CPLD-verilog SDRAM write control of the source code, development FPGA/CPLD
CPLD--fpga
- VHDL高级应用技巧 设和深入学习VHDL者-Senior VHDL application skills and in-depth study and VHDL are based
TAXI
- 收录大量的出租车计费系统设计的资料 基于CPLD FPGA的设计抱过设计报告-Contains a large number of taxi billing information system design based on CPLD FPGA design report hug
LCD12864
- lcd12864程序，采用Verilog语言编写，在CPLD开发板上经过验证，正确无误，实现显示英文的功能，希望对大家有用-lcd12864 procedure for the Verilog language, proven in the CPLD development board, correct, implement the function displayed in English, we hope to be useful
Writing_Testbench
- 是基于CPLD/FPGA的硬件开发环境测试文本编写的优秀书籍，其语法格式更加接近于C，适合入门者使用-verilog is based on CPLD/FPGA hardware descr iption language, its syntax is closer to C, suitable for beginners to use
FPGA-CPLD-
- FPGA-CPLD-开发流程 详细的讲解开发的过程-FPGA-CPLD-development process
elecfans.com-Altera
- 利用QUATUS实现CPLD FPGA 等设计流程,书籍介绍非常详细.希望大家阅读.-Using QUATUS achieve CPLD FPGA design flow, etc., Book is very detailed. Hope you read.
cpld
- 用FPGA实现简易数字示波器，分频，触发，以及，计数-FPGA implementation using simple digital oscilloscope, frequency, trigger, and, counting
FPGA-CPLD
- FPGA/CPLD设计经验分享，数字电路设计中的经典问题分析，很实用。-FPGA/CPLD design experience sharing, digital circuit design of the classic analysis, it is practical.
1
- 手把手教你学CPLD／FPGA设计（一）Taught you learn CPLD / FPGA design (a)-Taught you learn CPLD/FPGA design (a)
2
- 手把手教你学CPLD／FPGA设计（二）Taught you learn CPLD / FPGA Design (B)-Taught you learn CPLD/FPGA Design (B)
3
- 手把手教你学CPLD／FPGA设计（三）Taught you learn CPLD / FPGA design (c)-Taught you learn CPLD/FPGA design (c)
4
- 手把手教你学CPLD／FPGA设计（四）Taught you learn CPLD / FPGA Design (D)-Taught you learn CPLD/FPGA Design (D)
5
- 手把手教你学CPLD／FPGA设计（五）Taught you learn CPLD / FPGA Design (E-Taught you learn CPLD/FPGA Design (E)
COUNT_ASYNC_4SUB
- 4位异步二进制减法计数器,利用QUARTUS II 9的CPLD/FPGA-4bit_count_asyn_sub
timing
- 对输入CPLD/FPGA特定口的前后两个脉冲间隔进行计数并输出-timing for the break of 2 impulses into the certain input of CPLD/FPGA and output
fifo_vhdl
- 基于fpga,cpld的异步FIFO的设计 用VHDL语言进行相关的功能模块设计-Based on fpga, cpld design of asynchronous FIFO associated with VHDL design modules
CPLD
- verilog编写的加减6路可逆计数器，用于FPGA对6路脉冲信号的计数-verilog written addition and subtraction 6 way reversible counter for FPGA on the 6-channel pulse count
logiclock_makefile
- 一个CPLD/FPGA的程序，初学者可以看看，应该有帮助的-Code for CPLD/FPGA,useful !
ADc
- 与单片机相比，用CPLD/FPGA器件更适合于直接对高速AD采样控制。本实验接口器件为ADC0809，根据ADC0809的工作时序使用CPLD产生该控制信号，CPLD启动AD转换后，得到的数据送至单片机并在PC机及数码管上显示AD转换结果。-Compared with the microcontroller, CPLD/FPGA devices more suitable for direct sampling control of high-speed AD. The interface of