搜索资源列表
cpu
- 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
freerisc8_11
- 一个基于VHDL 的简单8位CPU的IP core核心代码-VHDL based on a simple 8-bit CPU core code of the IP core
exp_cpu
- CPU代码-VHDL语言,实现了CPU的基本功能。-CPU code-VHDL language, the realization of the basic functions of the CPU.
RISC
- hrisc cpu,为何只有vhdl选择呢?大家都用verilog的啊-hrisc cpu why only VHDL choice? We all use the Verilog ah
ram_old
- 用来测试cpu的ram代码 其中包括几十条指令 cpu的vhdl也在本站有下-Cpu the ram used to test the code, including dozens of VHDL cpu instructions also have a website under the
jamcpu
- jam CPU模拟器的设计与实现.其中包含设计文档-jam CPU Simulator Design and Implementation. which includes design documents
32bit_RISC_CPU
- 32 risc cpu的参考设计,内涵完整的testbench-32 risc cpu s reference design, the connotation of complete Testbench
IP_CORES
- IC内核的设计源码!其中包含MP3内核,CPU内核,I2C内核等多达式种IC设计的源码!-IC design of the kernel source code! MP3 contains one of the kernel, CPU core, I2C kernel up-type species such as IC design source!
cpu
- this file is cpu code in vhdl
cpu_behav
- this file is cpu code in vhdl
The_design_of_MIPS_CPU(VHDL)
- MIPS CPU设计实例的完整文档,台湾一个大学生的MIPS CPU完整设计文档,内附设计代码。-a complete document of MIPS CPU design , a Taiwan university students complete MIPS CPU design document, containing the design code.
n2cpu_nii51004
- NIOSII CPU设计实例,包括AVOLON总线特点和时序要求-NIOSII CPU design examples, including AVOLON bus characteristics and timing requirements
CPU
- RC4 Encrpytion 1.Encrpyt strings 2.Create pairs of keys for encoding and decoding automatically 3.Present the crptograph 4.Decode the crptograph to get the plaintext -This CPU has basic instruction set, and we utilize its instruction set
Microprocessor
- 精通verilog HDL语言编程的一个不错的cpu 代码-Verilog HDL language proficiency of a good cpu code
cpu
- 32位元浮点CPU,用VHDL语言以类似组合语言的方式写成-32 floating-point CPU(VHDL)
cpu
- 16位元浮点数CPU,可作运算,以VHDL编写-16-bit floating point CPU, can be used for computing in order to prepare VHDL
CPU
- CPU编程,比较低层的硬件编程的 chm 资料文件--
computer6
- 8位CPU软核设计与应用研究-8-bit CPU design and application of soft-core research .......
computer12
- 基于FPGA的八位RISC CPU的设计-FPGA-based RISC CPU design eight ....
dlx
- DLX CPU VHDL CODE UNIVERSITY