搜索资源列表
test_ddr2_ip
- ddr2 SDRAM 高性能控制器及测试-DDR2 SDRAM High Performance Controller
ddr3
- VHDL code sample.this files is the VHDL code for using of DDR3 and DDR2 SDRAM.
cdanpianji
- 红色飓风四代 altera DDR2 FPGA 开发 -FPGA development DDR2
ddr2_mem
- DDR2 xilinx ipcore 头文件 可以进行读写DDR2操作的接口! 读写时注意 按照时序控制进行!-DDR2 xilinx top file, you can read or write DDR2 interface。 attention:please control it !
MICRON_2048Mb_ddr2
- MICRON DDR2 SDRAM芯片Verilog仿真模型以及器件编号说明
Lab0201_ddr
- DDR2 数据存储实验,学习用 Code Composer Studio 观察、修改、填充 DSP 内存单元的方法-DDR2 Experimental data storage
ddr2readwrite.tar
- DDR2的调试代码,可以用于DDR2的调试,是可以用的,只需要设置一些参数就行。-DDR2 debug code that can be used for DDR2 debugging, it can use, only need to set some parameters on the line.
images
- Axon DDR2 device driver for Linux v2.13.6.
DDR2_Layout
- DDR2布线规则,中文版,对pcb排版有帮助-DDR2 routing rules, the Chinese version of the pcb layout helpful
Xilinx_DDR2_IP_TEST
- 本文档对Xilinx 公司FPGA开发环境中ISE中如何调用DDR2 IP进行了详细的说明。直接例化IPCORE,采用无TESTBENCH,无PLL的方式.-This document FPGA from Xilinx ISE development environment how to call DDR2 IP for a detailed descr iption. Direct instantiation IPCORE, no-TESTBENCH, no PLL ways.
Xilinx_DDR
- 本文档对ISE开发环境利用MIG调用DDR2 IP CORE进行了进行了详细的介绍,对初学者很有帮助。其中FPGA芯片为Xilinx公司SP6 FPGA, DDR2 内存为Micron 公司的一款 R2 MT47H128M8 芯片。-This document calls ISE development environment using MIG DDR2 IP CORE conducted a detailed descr iption, very helpful for beginners.
ddr_ddr2_sdram-ip
- 该程序为Altera 公司 DDR DDR2 SDRAM 的IP源程序安装包,非常有价值的东西,借此网址共享下。-The program for Altera Corporation DDR DDR2 SDRAM of IP source installation package, a very valuable thing, whereby the URL Sharing.
ddr2
- Functions for global dcache flush when writeback caching in SMP for Linux v2.13.6.
512MbDDR2
- DDR2的用户手册,需要的同学可以下载,在实际应用中很重要-DDR2 user manual, students need to be downloaded, it is important in practical applications
DDR2_XILINX
- xilinx FPGA设计需要的DDR2文件,可以应用于实际设计中-xilinx FPGA design needs DDR2 files that can be applied to the actual design
ddr2_defs
- C-code for register scope ddr2.
Cali
- 时间交替并行ADC相位误差、偏置误差、增益误差的校正,ddr2 sdram内存条的控制,基于visual dsp-phase, offset and gain error calibration of time-interleaved ADCs, ddr2 sdram controlment
DDR2Controller
- DDR2 SDRAM Control Verilog RTL Code
DE4_230_DDR2_UniPHY_QSYS
- DE4系列开发板关于ddr2在Qsys系统搭建的实例,有一定参考价值,。-DE4 series development board on the DDR2 in the example of Qsys system, has a certain reference value,.
4077mt48lc32m16a2
- 美光公司提供的DDR2的verilog仿真模型和do文件-Micron DDR2 provides the verilog simulation model and do file