搜索资源列表
DDR3-SDRAM-Verilog-Model
- 官方网站的verilog语言描写的ddr3 sdram仿真模型。各种型号可选。
intr_priority_control
- 多种数据缓存ddr3，乒乓缓存优先级判断，优先将缓存紧急的数据类型读出ddr3.(A variety of data cache DDR3, table tennis cache priority judgment, priority will cache urgent data type read ddr3.)
11_ddr3_test
- fpga ddr3 sdram verilog 黑金的板子(fpga ddr3 sdram verilog)
ddr3_rw_ctrl
- verilog基于DDR3 xilinx IP核 的DDR3的读写控制，方便学习(it is based on DDR3 IP core of xilinx)
Micron_Memory_DDR_SDRAM
- ddr3 封装库 采用粉末冶金法制备了微米尺寸和准纳米尺寸的氧化镧粒子增强钼合金。(ddr3 package The molybdenum alloy reinforced by lanthana particles with the sizes of nanometer and micron was prepared by powder metallurgy)
ddr3control
- 8位突发长度，一次64bit数据读写，MIG核(DDR3 controll implimention)
11_ddr3_test
- Xilinx Spartan-6 DDR3 test code
ddr3_test_top
- DDR3 test code 測試用的代碼 學習用,簡單的使用DDR3(DDR3 test code for learning verilog code study.)
ddr3_128
- DDR3 读写操作，使用spartan6平台验证。(DDR3 read and write operations,the use of spartan6 platform validation.)
evm816x_test
- 该代码功能是在CCS上实现DM8168的各个核心模块的检测，例如：DDR3测试等。(The function of the code is to realize the detection of each core module of DM8168 on CCS, such as: DDR3 test, etc..)
ddr3_test
- ddr3相关代码和基于ISE仿真调试，板级调试(DDR3 related code and simulation debugging based on ISE, board level debugging)
Verilog_1Gb_DDR3_G_Die
- ddr3控制器，速率可达1Gbps，语言使用verilog，已经加入tb(ddr3 controller, can be used to ddr3 control,high speed)
11_ddr3_test
- spartan6 ddr3 test with FPGA communicate
JESD79-3F-2
- 内容是pdf格式的ddr3的协议文档，仅供参考，不需要的请绕过，谢谢(The content is the PDF format of the DDR3 protocol document, for reference only, do not need to bypass, thank you.)
归档
- ddr3使用教学(DDR3 using teaching)
DDR3_A4
- xilinx FPGA A7 驱动DDR3的DEMO例程(DEMO routines driven by Xilinx FPGA A7 for DDR3)
09_ddr3_test
- 利用vivado的MIG控制器来实现DDR3的读写(Using vivado's MIG controller to realize DDR3's read and write)
S02《Artix7修炼秘籍》MIG_DDR内存应用
- artix 7系列 fpga mig ddr3应用教程(Artix 7 Series FPGA MIG DDR3 Application Tutorial)
spartan6 ddr3 controler
- xilinx spartan6 ddr3 test demo
test_ddr3
- 基于XILINX K7系列FPGA实现5120*5120分辨率20帧的DDR3读写，发送到海思3559,HDMI显示。(Based on Xilinx K7 series FPGA to achieve 5120*5120 resolution of 20 frames of DDR3 read and write, sent to the Hays 3559,HDMI display.)