搜索资源列表
Sawtooth_Wave
- verilog写的锯齿波程序，基于DDS原路的。内含testbench仿真文件。功能十分强大-verilog write sawtooth program, based on the same route of DDS. Embedded testbench simulation files. Is very powerful
six_wave
- 产生六种波形的DDS信号发生器，用verilog实现，有modersim仿真程序和结果，产生正玄波，方波，锯齿波，三角波，阶梯波。实现完全可用-the dds can output six signal，write in verilog。
CfgDDS_9910
- dds ad9910配置的verilog hdl程序，模块化设计，输入待配置的数据，字长，启动信号，即可自动产生时序，完成一次配置，模块还有done握手信号，方便用户调用时，反复多次配置。-dds ad9910 configuration verilog hdl program, modular design, the input data to be configured, word length, the start signal, the timing can be automatical
QAM_verilog
- 基于FPGA的16QAM，用verilog编写，其中DDS为自己编写，含设计文件和testbench。已通过moldesim软件仿真。 -FPGA-based 16QAM, with verilog writing, including DDS for their preparation, including design files and testbench. Simulation software has been through moldesim.
squre_generate
- 该程序使用Verolog HDL 语言编写，是一个使用DDS原理产生方波的程序，该程序还提供三个按键来改变频率。-This program is developed by Verilog HDL, and is used to generate a squre waveform of any frequancy. This program provide three buttons to change the frequency.
eetop.cn_dds
- 基于verilog的DDS设计,内附代码,仿真环境等说明-the DDS design based on verilog
DDS_TEXT1_1.1
- dds用Verilog代码实现，很适合做信号处理的同学借用。-DDS with Verilog code, it is suitable for signal processing of the students to borrow.
DDS_sin
- 这是一个用Verilog编写的以实现DDS功能的程序，包含了正弦、方波、锯齿波。-This is a Verilog written procedures to implement DDS functions, including sine, square wave, sawtooth.
DDDDDDDDDSSS
- FPGA实现DDS正弦波、方波、三角波发生器Verilog程序（已验证）Quartus工程文件-FPGA realization DDS sine, square, triangle wave generator Verilog program (verified) Quartus Project Files
vftvdr
- 基于FPGA的DDS信号发生器设计，包含Quartus 的工程，打开即可使用，Verilog 语言编写！-The DDS signal generator based on FPGA design, including the Quartus project, open to use, Verilog language! 朗读 显示对应的拉丁字符的拼音 字典- 查看字典详细内容-FPGA design, including the Quartus project, open to use, Ve
dac_900
- DAC900芯片驱动的Verilog语言描述，亲测可用。另外的是FIR滤波代码和DDS波形发生器的代码。既可单独使用，也可以整合在一起。-DAC900 chips driven Verilog language descr iption, pro-test available. Another is the FIR filter code and DDS waveform generator code. Either used alone or can be integrated.
Gen_Square
- 利用DDS技术产生100~1MHz的方波 利用DDS技术产生100~1MHz的方波-generate 100Hz ~ 1MHz square with DDS,using verilog HDL generate 100~1MHz square with DDS,using verilog HDL generate 100~1MHz square with DDS,using verilog HDL
dds_generater
- 波形发生器，可以生成正弦波、三角波、方波、锯齿波；可以选择输出频率和幅度，基于DDS设计，verilog和QuartusII开发-Waveform generator can generate sine, triangle, square wave, sawtooth wave you can the output frequency and amplitude, DDS-based design, verilog and development QuartusII
FPGA_phase_lock_demodulation
- FPGA 用Verilog语言实现数字锁相解调系统，包含了正交的DDS函数发生器和相应的AD驱动-FPGA digital demodulation system in Verilog lock, comprising a DDS orthogonal function generator and driving the corresponding AD
DDS_BPSK
- 基于DDS的BPSK调制器设计Verilog源码- U57FA u4E8.08 u868
sin
- 能够实现正弦波的输出以及通过频率控制字与相位控制字控制正弦波的相位与频率。(The output of the sine wave can be realized and the phase and frequency of the sine wave can be controlled by two control words.)
dds_rom
- 基于查找表的DDS的Verilog实现，分为相位累加器模块、ROM模块和顶层DDS模块(Verilog implementation of DDS based on lookup table)