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dds
- dds 驱动 ad9851 fpga vhdl-ad9851 dds ad9851 fpga vhdl
DDS_FINAL
- My project is on Direct Digital Synthesiser using Verilog HDL.This project is doing by me on july 2009 in summer training at NIT Kurukshetra, India. This DDS system generate the square wave, Triangular wave,Sine wave and saw wave with different fre
dds
- 这是用VERILOG描写的一个DDS的实例,涉及到一些lpm的运用希望对大家有用-it‘s useful。
dds_final
- 使用Verilog HDL语言实现的一个DDS,可以发生0-10Mhz正弦波、方波、三角波,频率步进可调,FM调制、AM调制,调制度可调。DA芯片为8位并行,160MHz-Using the Verilog HDL language implementation of a DDS, can occur 0-10Mhz sine, square, triangle wave, frequency step tunable, FM modulation, AM modulation, adjusta
DDS_Set
- AD9852,DDS芯片接收数据逻辑。(Verilog语言)-AD9852, DDS chips receive data logic. (Verilog language)
DDS
- 在FPGA中实现频率源的设计,使用硬件描述语言加以实现。-design DDS with verilog language
dds
- 用Verilog语言实现基于dds技术的余弦信号发生器,其输出位宽为16比特-Dds with the Verilog language technology based on the cosine signal generator, the output bit width is 16 bits
DDS__FPGA
- 基于FPGA的DDS信号发生器设计,包含Quartus 的工程,打开即可使用,Verilog 语言编写!-The DDS signal generator based on FPGA design, including the Quartus project, open to use, Verilog language! 朗读 显示对应的拉丁字符的拼音 字典- 查看字典详细内容
ddsfinal1
- verilog语言实现的dds代码,并行通信,生成四种波形,大赛编写的代码,modelsim仿真-verilog language dds code,modelsim debug
dds
- 采用verlog编写的tlc5615驱动程序,并利用了rom核实现了dds功能-Using verlog written tlc5615 driver, and use the rom-core functions to achieve a dds
Verilog-dds
- 用Verilog实现的DDS,直接频率合成器,相位可调。-Verilog DDS generator
DDS-Verilog-design-and-simulation
- DDS的Verilog设计及QuartusⅡ与Matlab联合仿真 -dds s verilog simulation dds s verilog simulation dds s verilog simulation dds s verilog simulation
DDS-VERILOG
- DDS的信号发生器verilog代码 可直接用于编程 已经测试-Verilog code of the DDS signal generator which can be used directly in the programming has been tested
DDS-MY-WORK-1
- FPGA模拟数字信号发生器DDS verilog-FPGA analog and digital signal generator DDS verilog
DDS-verilog
- DDS是直接数字式频率合成器(Direct Digital Synthesizer)的英文缩写,是一项关键的数字化技术。与传统的频率合成器相比,DDS具有低成本、低功耗、高分辨率和快速转换时间等优点,广泛使用在电信与电子仪器领域,是实现设备全数字化的一个关键技术。文件写了一个DDS的例程,并编写了TB文件。-DDS is a direct digital synthesizer (Direct Digital Synthesizer) of the English abbreviation, i
dds(1)
- 基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)
DDS波形发生器
- DDS波形生成器verilog语言书写(FPGA型号cy4以上)(DDS generate verilog)
DDS
- 描述了verilog实现的DDS信号发生器,可以经过FPGA验证,包括了代码实现以及书写。代码可以经过altera的EDA工具进行了验证,可以实现信号发生器的基本功能。希望大家珍惜,并好好学习。(Describes the Verilog implementation of the DDS signal generator, which can be verified by FPGA, including code implementation and writing. Code can be
dds
- 基于DDS的信号源设计(包括三角波、正弦波、方波)(Design of signal source based on DDS)
DDS的VERILOG原代码
- 实现了DDS的verilog源代码,可以使用(ajhsjdhjkshfjhfsjkjksa)