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cordic
- 该程序使用Verilog语言，可以生成dds正余弦信号-The program uses the Verilog language, can generate sine and cosine signals dds
dds
- 包含完整的dds产生的Verilog程序和test 文件-Contains the complete dds generated Verilog program and test files
Verilog
- ：Verilog实现的DDS正弦信号发生器和测频测相模块-: Verilog implementation of the DDS sine signal generator and frequency measurement module test phase
Verilog_FPGA_DDS
- Verilog编写基于FPGA的DDS实现-FPGA-based DDS Verilog
DDS
- 数字频率计 DDS，使用Verilog编写-Digital frequency meter DDS, prepared using the Verilog
cordic
- Cordic algorithm implementation in verilog for use in DDS
DDS
- 在MAXPLUSII下开发的基于verilog的直接数字频率合成器-Developed under the MAXPLUSII verilog-based direct digital frequency synthesizer
dds_quicklogic
- dds 源代码 verilog 很有意义-dds dds verilog source code makes sense
DDS
- 在ISE环境中，运用verilog语言实现DDS（直接数字式频率合成器（Direct Digital Synthesizer）的英文缩写）的功能-In the ISE environment, use verilog language DDS (direct digital frequency synthesizer (Direct Digital Synthesizer) in abbreviation) of the function
dds
- dds的verilog实现 调用dds核 已经实验验证-dds 调用dds核
dds
- 基于Verilog HDL的DDS设计与仿真-Verilog HDL-based design and simulation of DDS
MY-DDS
- 利用altera公司的FPGA使用verilog语言实现DDS功能 外加DA 可将数字信号转换成标准正弦信号-Altera FPGA use verilog language of DDS functions plus DA converts digital signals into a standard sine signal
DDS-design-based-on-verilog
- 用verilog语言设计DDS数字频率合成器-DDS design based on verilog
dds
- 使用AD5559,结合quartus中的硬件描述语言,实现了雷达发射信号二相码信号-using AD9959 and combining with verilog to output a rada signal of Binary code
DDS-frequency-synthesizer
- 本文主要讨论了Verilog语言的基于DDS的波形发生器的设计。从设计要求入手，本文给出了DDS的详细设计过程，包括各个模块的设计思想，电路图，Verilog语言程序代码。其大致思想为通过频率控制字和相位控制字去控制正弦函数的ROM存储表的地址并对应着得到其幅度值，最终达到输出需要波形的目的。-This paper mainly discusses the design of the Verilog language, the DDS-based waveform generator. Star
DDS-SIN
- 用verilog语言实现DDS的正弦波发送-DDS sine wave sent verilog language
DDS
- 基于verilog的DDS设计验证与仿真源代码，在quartus上实现，下载仿真成功-Based on the the the verilog DDS design verification and simulation of the source code, in quartus download simulation success
DDS
- DDS正弦波发生模块 基于verilog语言实现 在cycloneii系列FPGA上经过验证 频率步进1khz 共有256个点-The DDS sine wave module based on verilog language achieve in cycloneii series FPGA proven frequency stepping 1khz 256 points
FPGA-DDS-algorithm
- 采用FPGA的DDS算法Verilog程序的实现-FPGA DDS algorithm Verilog program implementation
DDS
- 直接数字频率合成器dds，用verilog实现，经过quartus验证-Direct digital frequency synthesizer the dds, used verilog achieved after quartus verify