搜索资源列表
DE2EP2C35F672
- DE2 EP2C35F672d的管脚分配图-DE2 EP2C35F672d pin allocation map
PaintBrush
- To use the device port ISP1362 and NIOS II CPU for mouse movement detection and the VGA interface and implement a Paint Brush Application[1] using Cyclone II FPGA on the Altera DE2 board.
DE2_lab_exercises
- Altera DE2 原装光盘附带 案例教程 手把手教 十个实验 verilog hdl/vhdl-DE2_labs_ exercise with verilog/vhdl
typewriter
- typewriter, shows characters on lcd about the keys from the de2 board.
FPGA
- 本文采用FPGA来模拟实际的乒乓球游戏。本设计是基于Altera 公司的FPGA Cyclone II 芯片EP2C35 的基础上实现，运用Verilog HDL 语言编程，Quartus II 软件上进行编译、仿真，最终在Altera 公司的DE2 开发板上成功实现下载和调试-In this paper, FPGA to simulate the actual tennis game. The design is based on Altera' s FPGA Cyclone II EP
de2
- 关于DE2开发板的资料 关于DE2较为全面的资料-Information on the DE2 development board ..
Lab3
- Display text to the LCD of a DE2 board
DE2_115_User_manual
- Altera DE2的开发板用户手册，对于系统设计人员很有借鉴作用-Altera DE2 development board user manual is useful for reference for system designers
DE2_70_VGA
- 在Quartus中，用de2-70开发板下载实现视频图像处理！很值得认真学习！-In the Quartus in development board with the de2-70 image processing for video downloads! Is worthy of serious study!
VHDL-0.1s-Timer
- 该程序完成了在altera de2 环境下实现0.1s新型计时器，该计时器可以运用于广大体育赛事中，有开关、暂停开始键、复位键。-The program completed the implementation in altera de2 0.1s under the new timer, which can be applied to the majority of sports events, a switch, pause start button, reset button.
VGA2
- VGA controller initialy designed for altera DE2 FPGA with 10 bits DAC. probably works with other systems if you have the correct clock source.
DE2
- terasic LTM+DE2 触摸屏例程-terasic LTM+ DE2 touch screen routine
DE2
- 竞赛内部资料，DE2为开发平台，对DE2的介绍十分详细-Competition within the data, DE2 platform for the development of very detailed descr iption DE2
cam
- It is a VERILOG program for interfacing the 5Megapixel camera module in ALTERA DE2 CYCLONEII board.
DE2_70_LTM_NIOS
- 基于DE2-70的数码相框，内含LTM控制模块，已调试，可用。-DE2-70-based digital photo frame, containing LTM control module, has been commissioning, is available.
VHDL-based-design-of-SPI
- 基于VHDL的串行同步通信SPI设计 本设计是用Quartus作为开发环境，以DE2板为硬件平台实现的SPI同步串行通讯。设计过程方便。根据接收和发送两个主要部分实现了SPI的基本功能。此外，该设计还实现了波特率发生器，数码管显示的功能。用DE2板实现具有电路简洁，开发周期短的优点。充分利用了EDA设计的优点。开发过程用了VHDL硬件描述语言进行描述，从底层设计，分模块进行，充分提高了设计者的数字逻辑设计的概念。-VHDL-based SPI serial synchronous comm
music
- 以vhdl 語言利用nios編寫的音樂控制範例.altera de2板實測可用-Vhdl language used to write the music control nios sample. Altera de2 board can be measured
DE2_CCD_detect
- de2,altera fpga开发板，自带的源码，ccd_detect-de2, altera fpga development board, comes with source code, ccd_detect
DE2-115_labs_vhdl
- 高品质音频编解码器WM8731的Verilog使用程序-High-quality audio codec WM8731 of Verilog using the program
Altera-Ball-Bouncing-Control.tar
- Altera DE2 Board VGA Ball bouncing Control