搜索资源列表
CuFIFO
- fifo的vhdl代码,比较简单，适合初学。-fifo the VHDL code, is relatively simple, suitable for beginners.
asyn_fifo
- verilog编写的异步fifo源代码，asyn_fifo.v为顶层，调用其他四个文件-asynchronous fifo prepared Verilog source code, asyn_fifo.v for top-level, call the other four documents
75448172geleicounter
- 这是异步fifo的vhdl实现代码，已经在FPGA上通过实践证明，运行状态良好-This is the asynchronous fifo realize the VHDL code has been adopted in the FPGA Practice has proved that running in good condition
bulkloop
- EZ-USB FX2 SLAVE FIFO模式固件代码-EZ-USB FX2 SLAVE FIFO mode firmware code
myfifo
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
myfifo_bb
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
myfifo_syn
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
myfifo_wave0
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
myfifo_wave1
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
FIFOinterface
- fifo(8):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
FIFO.OPT
- 操作系统课程设计（源码和报告） 请求页式管理缺页中断模拟设计--FIFO、OPT-Operating systems curriculum design (source code and reports) request page management page fault analog design- FIFO, OPT
fifotop
- 基于FPGA编写的VHDL语言，FIFO代码程序。 程序完整。-VHDL-based FPGA written language, FIFO procedure code. Complete the procedure.
gencontrol
- 高速任意波形产生器控制模块 控制NCO,FIFO，并串转换-hign-speed wfgenerator control
fifo_ptrs_gray
- fifo pointers in verilog gray code utilization for synchronius
VHDL06
- 16×4bit的FIFO设计代码，学习代码，请在下载24小时后删除。-16 × 4bit the FIFO design code, learning the code, please delete after 24 hours to download.
FIFO
- VHDL code for first in first out register
fifo1k_32
- PCI 数据采集控制卡的内部 FIFO处理代码-Data Acquisition and Control Card PCI internal FIFO handling code
8fifo
- 可综合的 8x8 fifo VHDL 源代码-Can be integrated 8x8 fifo VHDL source code
FIFO
- 利用Verilog实现了一个FIFO，包含几个模块文件，适合初学Verilog的朋友，含测试代码。-Verilog achieved using a FIFO, a document contains several modules, suitable for novice Verilog friends, including test code.
fifo_sync
- 用VHDL语言编写的FPGA程序,实现异步FIFO的功能。这个程序设计十分巧妙，精简。 -vhdl fifo sound code