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一个32位元的浮点数加法器,可将两IEEE 754格式内的值进行相加,A 32-bit floating-point adder can be both within the IEEE 754 format to add value
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浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算,结合vhdl和EPGA可编程技术,完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
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Implementation of 32-bits Floating Point Adder, based on IEEE 754 Standard
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能够实现单精度浮点加法运算。输入引脚有:第一运算数,第二运算数,复位信号,时钟信号。输出信号有:运算结果,运算完成标志。(To achieve a single precision floating-point addition operations)
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