搜索资源列表
dds_vhdl
- fpga VHDL语言,控制DDS产生频率可变的正弦波信号扫频-FPGA VHDL DDS
DDSVerilog
- DDS Verilog 代码。包含英文文档说明-DDS Verilog code. Containing the English documentation
dds
- 基于FPGA和DDS的正弦信号发生器程序-Based on FPGA and DDS sinusoidal signal generator program
FPGA_DDS
- 基于Cyclone EP1C6240C8 的AD9854 DDS的接口程序,使用FPGA来控制DDS信号的产生,从而达到高频信号产生的目的。 通过FPGA口线模拟AD9854的控制时序。 提供DDS信号波形变换、DDS频率调整、DDS内部比较器使用等功能。-Cyclone EP1C6240C8 of the AD9854 DDS-based interface program, use the FPGA to control the DDS signal generation, so a
dds
- 用vhdk编写的dds信号发生器的代码,用fpga实现dds功能-Dds with vhdk signal generator written in code, using fpga implementation dds feature
DDS
- 用FPGA实现的DDS信号发生器(ALtera的)-DDS signal
DDS1-2
- 利用FPGA设计一个直接数字频率合成器(DDS),要求能够通过键盘设定输出正弦波、三角波和方波,输出波形频率由键盘输入设定,液晶显示屏显示输出波形类型和频率,输出频率范围10Hz-20kHz,步长0.5Hz。-FPGA design using a direct digital synthesizer (DDS), requires the ability to set the keyboard output sine wave, triangle wave and square wave ou
ad9958
- AD9958是一款功能强大的DDS芯片,是AD公司新上市的产品,能够产生标准信号已及线性调频,非线性调频等信号。-AD9958 is a new chip with much more greater function.It is very suitable in signal processing. It can generate kinds of signal format such as standord signal and lfm signal.
DDS_generation
- 基于Altera FPGA的DDS 模块 - DDS generation module based on Altera FPGA
MyDDS
- 利用查找表法编写的DDS的verilog程序,节省了利用IP核实现需要的资源,软件为ISE,-Prepared using look-up table method of verilog DDS program, save the use of IP core implementation requires resources, software for the ISE,
helpfpga
- VHDL语言 用FPGA实现DDS数字频率合成器 包括正弦波和方波-FPGA implementation using VHDL, DDS digital frequency synthesizer, including sine and square wave
FPGA_DDS
- 基于FPGA的DDS信号发生器产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-FPGA-based VHDL source DDS signal generator and the test stimulus file matlab model simulation in modelsim adopted under
S3_WAVE
- 实现正弦波输出的DSS,在逻辑分析仪上仿真,能够真确实现功能-input DDS ,Sine wave output of the DSS to achieve FPGA-based,Simulation results using the logic analyzer fully meet the requirements
DDS
- 用FPGA实现数字频率合成的源程序,ALTERA公司芯片。-A DDS program with Altera chip.
sin5
- DDS FPGA 正弦波 VHDL语言-DDS FPGA 正弦波 VHDL语言
sin7
- DDS FPGA 正弦波 VHDL语言-DDS FPGA 正弦波 VHDL语言
DDS
- 基于FPGA的DDS的相位累加器详细介绍,是VHDL编程,利用quartus2平台.-Design of Direct digital synthesis Signal Generator
dds_using_FPGA
- 用FPGA实现的DDS,简单实用,通过调试-Implemented with FPGA DDS, simple and practical, by commissioning
DDS_Set
- AD9852,DDS芯片接收数据逻辑。(Verilog语言)-AD9852, DDS chips receive data logic. (Verilog language)
dds
- vhdl编写,利用fpga完成了dds发生器的功能-vhdl prepared using fpga complete function generator dds