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chunchuqidesheji
- 在计算机系统中，一般都提供一定数量的存储器。在用FPGA实现的系统中，除可以使用FPGA本身提供的存储器资源外，还可以使用FPGA的外部扩充存储器。本实验要求设计一个32×8 RAM，如下图所示，它包含5位地址、8位数据口和一个写控制端口。-In the computer system, generally provide a certain amount of memory. FPGA implementation of the system in use, unless you can us
using_the_LUT_as_distributed_RAM_in_Spartan-3_FPGA
- 在 Spartan-3 系列 FPGA 中将查找表用作分布式 RAM-using_the_LUT_as_distributed_RAM_in_Spartan-3_FPGA
m_decoder
- 恢复以曼彻斯特编码格式输入的mdi信号成实际数据并存储在双端口RAM后以中断方式通知DSP读取数据，所需双端口RAM程序可以从相应的FPGA编译系统中产生-A return to the Manchester encoded signal is input into the actual data mdi and stored in the dual-port RAM notify the DSP after the break to read the data, the required du
m_encoder
- 将写入的数据用曼彻斯特码格式从meout口输出，所需内部存储单元可根据所使用不同的FPGA类型由相应的编译软件产生所需双端口RAM模块-The data will be written by Manchester code format from meout port output, the required internal storage unit can be used according to the different types of FPGA Compiler software f
vlsiram
- VHDL RAM 16 * 8 source code FPGA
MATLAB_HexToMif
- 将Hex格式的数据转成Mif格式，供FPGA搭建系统时初始化RAM.-Hex format data will be converted into Mif format for initialization when the FPGA set up the system RAM.
rea_wri_ram
- 用FPGA实现对RAM的读写，实现特定的功能-FPGA implementation of the RAM with read and write, to achieve a specific function
NET2
- This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, usi
The-pulse-signal-generator
- 脉冲信号发生器：采用DDS技术实现脉冲信号的周期、脉冲宽度、幅值的数控调节。通过单片机与FPGA的并行通信技术将频率控制字及矩形脉冲数据传送给FPGA的双口RAM。模拟输出通道则将信号通过100MHz、8位D/A转换器将波形数据转换成模拟脉冲信号，最后通过高速运放构成的放大器放大，实现幅度连续可调。-The pulse signal generator: using the DDS technology to achieve the pulse signal cycles, pulse widt
RAMaddressGenerator
- 基于FPGA（EP2C5T144开发板）的RAM的地址发生器，初学者适用-Based on FPGA (EP2C5T144 development board) RAM address generator for beginners
RAM_test
- ADSPTS201相关程序，总线方式、DMA方式读写片外SDRM和FPGA内部RAM数据 -ADSPTS201 procedures, the bus mode, DMA mode and the FPGA to read and write chip internal RAM data SDRM
DoubleRAM
- actel fpga kit 双端口RAM 实验-actel fpga kit dual-port RAM test
ram_fpgavhdl
- fpga vhdl实现一个标准双端口ram，可以作为单端口或者双端口用 -fpga vhdl achieve a standard dual-port ram, can be used as a single port or dual port with a
m4k-example
- FPGA中M4K的使用例子，比如rom ram-the example to useing M4K in FPGA
PseudoHC11_MCU
- This extensive proyect turns an FPGA or CPLD into an HC11 simulation. It takes in various opcodes and performs several 8bit operations. The package includes an ALU, UART, RAM module, LCD display and 7 segments as well.-This extensive proyect turns an
ygyTest
- 利用开源网站上的8051核，在Spartan 3A开发板上实现成功，开发环境是Xilinx ISE Design Suite 12.3，顶层文件基于原理图开发，扩展了外部ROM和RAM，且更改了地址宽度-implment the mc8051 IP in spartan-3A FPGA starten kit.
spram
- 基于altera fpga 的单口ram ip核的应用实例，包含整个工程和moselsim仿真，数据，写使能，地址都是用模块来产生的。-Altera fpga single port ram the ip core application instance, contains the entire engineering and moselsim of simulation data, Write Enable, addresses are generated by the module.
cpu
- 用FPGA实现了CPU中RAM,ROM等功能，设计比较完整-FPGA Implementation of a CPU, RAM, ROM, function, design is more complete
Port-RAMs
- 介绍双口ram功能，进一步了解在fpga上怎么设计一个双口ram-Introduced the dual-port ram function to learn more about the fpga on how to design a dual port ram
FIFO
- FPGA内设计同步FIFO和异步FIFO，以及双口RAM的方法,FIFO设计的经验之谈，非常经典。-Synchronous FIFO and asynchronous FIFO, and dual-port RAM within the FPGA design,FIFO design rule of thumb, very classic.