搜索资源列表
LIP1741CORE_dvd_fsm
- LIP1741 DVD FSM Verilog source code
fsm
- android工单系统初期的用户登录，自动登录，用户管理，GPS定位，本地SQLITE数据库处理等功能-the initial user login the android work order system, automatic login, user management, GPS location, local SQLITE database processing functions
sequence_detect
- 串行数据检测器，检测数据中是否存在10010，用FSM编写，在modelsim中仿真通过，功能上符合要求-Serial data detector detects data exists 10010, with FSM write, through simulation in modelsim functionality required
fsm
- errors are coloured thanks again for the good response
simple_fsm_moore_3_always_best
- 三段式moore FSM状态机源码的标准实现方法-3 section moore FSM source code
callbacks
- Callbacks for the FSM driver for Linux.
fsmd_examples
- fsm有限状态机加datapath的一个例子-fsm finite state machine plus datapath example
soda-vending
- 通过fsm实现汽水贩卖机投币，选择的基本功能，尚未实现找零和设置，通过测试。-By fsm soda vending machine coin selected basic function, and yet achieve the homing and setting, by testing
usart_resolve
- 基于状态机思想的串口命令解析，单片机使用stm32-resolve a message from usart using FSM,the MCU is stm32
USart_message
- 基于状态机思想的串口命令解析，单片机使用stm32-resolve a message from usart using FSM,the MCU is stm32
fsm
- Finite state machine driver for Linux.
hdlsrc
- In mathematics, the greatest common divisor (gcd), also known as the greatest common factor (gcf), or highest common factor (hcf), of two or more integers(at least one of which is not zero), is the largest positive integer that divides the numbers wi
FSM
- 使用频域平滑的方法来实现信号循环谱估计的算法-The smooth frequency domain signal cyclic spectrum estimation algorithm
FSM
- Finite state machine
moore-FSM
- 该程序描述并且模拟和实现了了一个摩尔有限状态机的功能和作用-The program describes the simulation and the function and role of a mole finite state machine
three-FSM
- 这个程序描述的是模拟并实现三个always的有限状态机的实例-This procedure describes the simulation and three always finite state machine instance
Mealy-FSM
- 这个程序描述的是模拟并实现了米里有限状态机的功能的实例-This procedure describes the simulation and Mealy finite state machine instance
fsm
- brief finite state machine source code.
FSM_3blocks
- 经典3段式有限状态的verilog HDL描述，在modelsim 中仿真通过。-A classical FSM of three paragrahs, which is described by verilog HDL and simulated in modelsim successfully.
Verilog-FSM(TSC)
- Finate State machine