搜索资源列表
CoreI2C
- 基于ACTEL公司Fusion系列芯片开发的嵌入式工程。实现了I2C功能，包括编写的Core。文件包括Libero开发的工程及Keil开发的工程。-Fusion Series ACTEL chip company based development of embedded projects. I2C capabilities realized, including the preparation of the Core. Documents include the development of
LPC900_SPI
- LPC900 FLASH单片机，是PHILIPS公司推出的一款高性能、微功耗51内核单片机，主要集成了字节方式的I2C总线、SPI总线、增强型UART接口、实时时钟、E2PROM、A/D转换器、ISP/IAP在线编程和远程编程方式等一系列有特色的功能部件。-LPC900 FLASH MCU is PHILIPS company introduced a high performance, micro-power 51-core chip, a byte-oriented major integr
i2c_latest[1].tar
- I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the consumer and telecom market sector and as a board level communications protocol. The OpenCores I2C Mast
TEA5767
- TE5767收音机模块与89S52单片机通信写频率程序，调试I2C总线的代码，实现收音机功能-is a process belonging to the Audio Core program . audiocore.dll is a DLL file used by Audio Core created by Microsoft Corporation "This process is still being reviewed. If you have some information abou
dm6437
- 基于TI达芬奇系列DSP-DM6437，通过I2C读写函数来配置视频解码芯片TVP5150中的寄存器，并通过配置DM6437内部视频处理前段VPFE和视频处理后端VPBE 中的寄存器实现了图像的高速采集和实时显示-With DM6437 of TI Company based on DaVinci as the core processor,a image high-speed acquisition and real-time displaying systemis completed aft
Hydrogen_Core51
- Hydrogen/C51 是一个用于51的非占先操作系统 基本上用纯 C 实现, 嵌入了大概10行的汇编 基本需求: 1.最小编译代码大概在 2.4k 2.需要使用片外的 xdata 作为堆使用 3.占用 TIMER0 作为计时 使用基本要求: 1.任务中必需要存在 Sleep/WaitFor 函数才能主动放弃占用CPU 2.任务入口和使用到Sleep/WaitFor的函数必需是 reentrant. 内核功能: 1.动态建立任务 2.支持事
i2cslave_latest.tar
- I2C Slave Core in VHDL
AT24C32
- 程序用M0内核实现从I2C读写AT24C32-Program M0 core from the I2C read and write AT24C32
i2c_master
- I2C master模式的IP core（verilog）-I2C master mode IP core (verilog)
IPCores_iic_8051
- I2C_IP_Core, 使用VHDL 和VERLOG编写，并有文档说明-I2C IP Core, VHDL/Verilog
stm32_i2c
- 使用STM32F103系列的ARM-CORTEX-M3内核的CPU进行I2C总线读取。涉及到STM32控制，及I2C总线控制。-Use STM32F103 series of ARM-CORTEX-M3 core CPU for I2C bus to read. Involves STM32 control, and I2C bus control.
I2s
- i2cSlave is a minimalist I2C slave IP core that provides the basic framework for the implementation of custom I2C slave devices. The core provides a means to read and write up to 256 8-byte registers. These registers can be connected to the users
i2c_core
- i2c ip core support slave and master mode
I2C_Slave
- I2C slave IP core，内含此IP core的完整code，详细的式样说明,详细的状态机说明-I2C slave IP core, include complete code of this IP core, and the detailed specification, the detailed FSM.
i2c_latest.tar
- i2C总线的控制器核，实现了I2C的主站功能。-I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the consumer and telecom market sector and as a board level communications protocol
i2c_slave_V1.2
- 在stm32单片机上，用IO口的上升沿和下降沿中断设计的I2C从机代码。测试通过。所有过程用状态机来控制，没有cpu空延时。 核心代码和单片机相关代码分开，方便移植。 主要用在项目验证和学习交流！-On stm32 microcontroller, with rising and falling IO port interrupt design of I2C slave code. The test. All the process is controlled by a state ma
I2C_Single_Master
- I2C Single master written in Verilog Libero Designer core generator.-I2C Single master written in Verilog Libero Designer core generator.
project3
- 本例程使用GPIO模拟I2C时序实现串行EEPROM的读写，并测试读写速度。 核心文件为： b i2c_gpio.c/.h ： I2C底层协议的实现代码（所有的I2C器件均可用） b eeprom_24xx.c/.h : 24XX串行EEPROM的驱动程序 demo_i2c_eeprom.c/.h : 演示EEPROM读写的主程序 修改SCL时钟频率的方法：修改b i2c_gpio.c中的函数 static void i2c_Delay(void)-
UART
- 周立功TinyM0配套基本外设例程，基于TinyM0核心板，UART示例程序-ZLG TinyM0 peripherals supporting basic routines, based TinyM0 core board, I2C example program
i2c_master_controller
- Verilig语言描述的I2C Mater控制器的IP核，已经过实践应用，适合于FPGA I2C接口设计应用。本IP核在Altera QII 15.1软件环境下综合，并且包含基于NiosII Gen2处理器的i2c软件驱动代码。-Verilig language I2C Mater described controller IP core, has been the practical application, suitable for FPGA I2C interface design app