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21840261RS(32to28)encoderanddecodervhdl
- (32,28)编码和译码程序 ，基于vhdl来实现的，并且在quartus中运行实现-(32,28) coding and decoding process, based on vhdl to achieve, and run to achieve in quartus
Quartus_CRACK
- Quartus_CRACK_license.dat破解文件，对初学软件的朋友有用。-Quartus_CRACK_license.dat crack file, be useful for beginners software friends.
VtoRGB
- Verilog写得BT656视频数据转为RGB数据的Quartus工程文件！-The verilog module for changing BT656 data to RGB data!
MCU_FPGA_62256
- 单片机控制FPGA实现62256的读写功能的程序，使用Quartus II平台进行开发。-Microcontroller FPGA to read and write functions to achieve 62 256 procedures, the use Quartus II development platform.
led_test
- LED测试程序工程文件,VHDL代码，在Quartus II 6.0中测试通过。-led vhdl test programe in Quartus II
cnt_test
- 用Quartus ii 6.0开发的计数器工程文件，用VHDL语言编写-Counter programe used in VHDL,devlopment tool:Quartus ii 6.0
tt
- 在Quartus中实现256的RAM(经过实际的应用验证).rar-Realized in the Quartus 256 RAM (after the actual application of verification). Rar
EDA
- 熟练使用vhdl语言，以及介绍了quartus和仿真软件，具体事例-Vhdl skilled use of language, and introduced quartus and simulation software, specific examples
QuartusII
- Quartus+II+中文教程 Quartus+II+中文教程-Quartus+II+中文教程
nios_shi
- 由nios ii实现的，用cfi flash与SDRAM共同实现的电子数字时钟，基于sopc的嵌入式代码，所用软件都是9.0版本的，包括quartus ii9.0 和nios ii9.0-Achieved by the nios ii, together with the cfi flash with SDRAM to achieve the electronic digital clock, based on sopc embedded code, the software is versio
VEDA7LED
- 采用QUARTUS II 7.2 (32-BIT)工具实现的两位7段数码管动态扫描显示的VHDL程序。硬件电路采用8位拨位开关控制，高四位控制左数码管，第四位控制右数码管。芯片采用EP1C6T144FPGA器件。-By QUARTUS II 7.2 (32-BIT) tools to achieve the two 7-segment digital tube dynamic scan showed the VHDL program. 8-bit hardware with dial-bit s
DAC0832
- 介绍了DA的vhdl语言.在quartus环境中-da vhdl
QuartusIITimequest
- 关于quartus中的Timequest Timing analyzer的讲解PPT，由Altera提供-About quartus in Timequest Timing analyzer' s explanation PPT, provided by the Altera
FFT
- 用VHDL语言建立了quartus工程，可进行dsp处理-VHDL dsp
DDS_GEN
- Functional Generator in DDS AD9953 (AD9954) Freq.: 1Hz....30MHz Out.: 2mV....2V Files: Project SCH&PCB - ORCAD 9.2 QUARTUS SRC for EPM570T100C5 IAR C SRC for AT91SAM7S64
tut_signaltapII_verilogDE2
- Altera公司原版设计手册，关于signaltap ii。-This tutorial explains how to use the SignalTap II feature within Altera’s Quartus R II software. The Signal- Tap II Embedded Logic Analyzer is a system-level debugging tool that captures and displays signals in
DE2_70_D5M_LTM_binary
- Quartus II的一个LTM现实例子-Quartus II real example of a LTM
Example-b4-1
- Altera基本宏功能的产生和实现方法.定制一个双端口RAM，DualPortRAM,Quartus II仿真器中做门级仿真,在ModelSim中对这个工程进行RTL级仿真.-Altera basic macro functionality of the generation and realization. Customize a dual-port RAM, DualPortRAM, Quartus II simulator to do gate level simulation, on t
lcd12864
- 用Verilog写得FPGA实现lcd１２８６４的控制程序，在Ｑｕａｒｔｕｓ环境下调试通过-Written using Verilog FPGA implementation lcd12864 control program, the debugging environment by Quartus
fadder32
- 短代码实现32位全加器，带经Quartus II9.1编程测试全部文件-Short code to achieve 32-bit full adder, with programming tested by the Quartus II9.1 all documents