搜索资源列表
Verilog
- 用verilog实现的电子日历程序,在Quartus II上编译通过-Implemented using verilog electronic calendar program, compiled by the Quartus II
CLOCK-ON-ALTERA-DEV-NOARD-RONTEX
- 这是我上电子线路设计课程时自己写的数字钟设计的整个工程.网上下载安装quartus II软件后双击clock.sof打开调试.若软件说没有权限,请删除db文件夹后再试. 文件夹中附带我的实验报告,其中详细讲解了我的设计思路\软件架构\可能出现的问题等等. 调试步骤就不讲了,管脚分配请网友自行完成. 开发板 Altera Cyclone II EP2C35F672C6 软件平台 Quartus II 语言 verilogHDL-These are all the project
fft
- Quartusii的FFT,使用Verilog HDL 语言的FFT-FFT based on Quartusii
fir_comm
- 用QUARTUS软件，实现一个32阶的FIR数字滤波器-QUARTUS software used to implement a 32-order FIR digital filter
xianbo
- 以DE2为平台，用QUARTUS软件实现一个数字陷波器-To DE2 as a platform, software with a digital QUARTUS notch filter
fir_da_test
- 用QUARTUS软件，用DA算法实现一个32阶的FIR滤波器-QUARTUS software used with the DA algorithm to achieve a 32-order FIR filter
USB_Blaster_WIN7_x64
- altera usb-blaster win7下驱动，经测试可用-altera usb-blaster win7 to drive, the test can be used
quartusHH
- 基于Quartus II的EDA时钟模块-Quartus II EDA based on the clock module
Verilog-IIC
- VerilogHDL语言编写的IIC 读写试验程序, 在Quartus II 8.1下面调试通过 -IIC VerilogHDL languages to read and write test procedures, the Quartus II 8.1 debugging through the following
verilog-PS2-Keyboard
- veirlog编写的PS2键盘通讯程序, 并有PS2接口的相关说明, Quartus II 8.1工程文件-veirlog written communication procedures PS2 keyboard, and a PS2 interface instructions, Quartus II 8.1 project file
miaobiao
- 秒表 数码管显示 采用verilog语言编写 Quartus II 9.0sp2 编译成功后生成的所有文件已包含-Digital display with stopwatch verilog language Quartus II 9.0sp2 successfully compiled all the files have been generated that contains
crack
- Altera full crack for quartus and nios
PLDs
- vhdl books a group of pdf book that shows how to design and build vhdl components and implement them in quartus -vhdl books a group of pdf book that shows how to design and build vhdl components and implement them in quartus
Altera_FPGA_CPLD_disign
- 学习FPGA的经典图书!书中既有对开发环境QUARTUS的详细讲述，又有对硬件语言的讲解！-Classic books to learn FPGA! QUARTUS book both the details of the development environment described, but also to the hardware language to explain!
fft_256
- 256点的fft，使用verilog硬件描述语言实现，可以在quartus等仿真软件仿真-failed to translate
file.vec
- 对QUARTUS进行功能仿真时，需要输入自定义或者matlab生成的信号，此文件就是仿真需要的向量文件（.vec）,格式固定，可以仿照这个写，内含说明-Functional simulation of QUARTUS, you need to enter a custom or matlab generated signal, this file is required simulation vector file (. Vec), fixed format, you can follow th
Quartus_II_sch_dev
- Quartus Ⅱ原理图输入法深入,难得的讲述Q II的原理图设计输入方法的文档！-Quartus Ⅱ schematic input depth, rare about Q II schematic design entry method of the document!
PN4
- 语言：VHDL 功能：该PN4序列的特点为将一个4位序列的前两位取异或，再让序列左移一位，用异或的结果作为序列的最后一位。序列周期是15，即15位伪随机序列。其中包括序列的产生模块和检测模块。对于误码检测，首先捕获相位。然后，规定测试的码的总个数，统计这些码中有多少个不能满足PN序列特点的，用计数器统计个数。如果发现误码过多，可能是相位失调，重新捕获相位，再进行误码检测。 仿真工具：modelsim 综合工具：quartus -Language: VHDL function:
SRAM
- 语言：VHDL 功能：利用VHDL编程，实现FPGA对SRAMIS61LV24516的读写操作。由于是针对IS61LV24516型号进行读写的，如果不是此型号的SRAM需要对程序进行时序修改。 仿真工具：modelsim 综合工具：quartus -Language: VHDL function: the use of VHDL programming, FPGA on SRAMIS61LV24516 read and write operations. Because it