搜索资源列表
IPcore
- 非常有用的IP核资源,里面包含了JTAG,MEMORY,PCI,SDRAM和USB1.1等内容,期望对大家有用-A very useful IP core resources, which includes the JTAG, MEMORY, PCI, SDRAM, and USB1.1 and other content, expectations for all of us
ddr_sdr_V1_1
- DDR控制器 - 用XILINX Virtex II FPGA实现 - 使用DDR MT46V16M16作为仿真模型 - 通用化-DR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted
UP_IP_Library_80
- altera大学IP库,包含ps2、sdram、rs232等-altera University, IP libraries, including the ps2, sdram, rs232, etc.
ddr_sdram_controller
- DDR SDRAM Controller design
control_interface
- sdram控制器i/o接口模块的VHDL源程序文件,可直接用-sdram interface
SDRAM
- SDRAM implemented using VHDL
SDRAM_VHDL
- VHDL SDRAM Controller
Sdram_Control_2Port
- 双端口SDRAM控制器,将SDRAM虚拟成两个端口,已经在ALTER DE2开发板的硬件上验证通过,采用Verilog HDL语言编写。-Dual-port SDRAM controller, SDRAM virtual into two ports, have ALTER DE2 development board hardware verification by using the Verilog HDL language.
memtest
- 在数字系统中,一般存在多个芯片,利用不同的特点用于实现不同的功能,一般都包含CPU,FPGA,AD,DA,memory,ASSP(专用标准模块),ASIC等。CPU用于进行智能控制,FPGA进行硬件算法处理和多设备接口,AD进行模数转换,DA进行数模转换,memory存储临时数据。因此,FPGA如何与其他芯片进行通讯是重要的设计内容。数据输入,数据输出,双向通讯,指令传递,地址管理,不同时钟的异步通讯问题等等都需要处理。最基本的MEMORY如SRAM(128KX8bbit静态存储器628128)
DE2_LCM_CCD_inverse
- DE2版自带的CCD驱动,将图像存储于SDRAM中-DE2 version comes with the CCD driver in the image stored in SDRAM
sdram_ctrl.tar
- sdram controller VHDL source code
CCD
- 本设计主要用来进行图像采集处理,通过摄像头采集图像信息,经过插值算法后存储到外部SDRAM,然后读取图像数据,进行边缘滤波处理后经VGA输出到屏幕上。-This design is mainly used for image acquisition and processing,through the camera capture image information,after interpolation to the external memory after the SDRAM,and th
ddr
- DDR SDRAM 控制器 VHDL代码,可支持32bits数据总线-VHDL code for DDR SDRAM controller, supporting 32bits data bus
XAPP134_SDRAM_VHDL
- XAPP134 SDRAM VHDL design file
mt48lc4m16a2
- 模拟micron的sdram的 VHDL 代码,用于验证自己的sdram控制器。-Micron sdram the VHDL simulation of the code used to validate their sdram controller.
RED--PCI-5.0
- 使用PCI9054作为接口芯片,通过FPGA实现PCI9054,SDRAM和AD之间的连接,本程序是以此为目的编写的.-PCI9054 interface chip used as a through FPGA implementation PCI9054, SDRAM, and the connection between AD, the program is prepared for this purpose.
source
- SDRAM控制器源代码,是ALTERA公司的IP源核,很好很强大-SDRAM controller source code, very very strong
SDR_SDRAM_IP
- SDR SDRAM 控制器,Altera官网重要资料。内涵说明文档,和VHDL与Verilog两种设计IP。-SDR SDRAM controller from Altera
model
- 用vhdl写的 ddr sdram 控制器,数据位可以修改。在quartus2下仿真通过-With written ddr sdram controller vhdl
sdr-sdram-controller-source-code
- altera 公司sdr sdram 控制器源码,是VHDL的,大家选择下载-The altera sdr sdram controller source, the VHDL, we choose to download