搜索资源列表
seqdetect
- sequence detector for static random access memory
schk
- 熟悉用状态机设计各种序列检测器的思路和方用状态机实现序列检测器的设计-Familiar with the various sequence detector state machine design thinking and to use the state machine to achieve the design of the sequence detector
s101
- 用VHDL语言，设计一个“101”序列检测器，双过程描述编写-VHDL language, to design a dual procedure describes the preparation of "101" sequence detector.
xu-lie-jiance-qi
- 序列检测器可用于检测一组或多组由二进制码组成的脉冲序列信号，当序列检测器连续收到一组串行二进制码后，如果这组码与检测器中预先设置的码相同，则输出1，否则输出0。由于这种检测的关键在于正确码的收到必须是连续的，这就要求检测器必须记住前一次的正确码及正确序列，直到在连续的检测中所收到的每一位码都与预置数的对应码相同。在检测过程中，任何一位不相等都将回到初始状态重新开始检测。 状态机的工作方式就是根据控制信号按照预先设定的状态进行顺序运行。本实验就是要求当检测器收到一组二进制码后，如果这组码与检
Digital-gates
- The controller and datapath for a sequence detector which is formed using the prepared library of gates like not, nand, etc. this library is prepared in c++.
work
- 这里面包含了从易到难的6个很经典的verilog例子，有序列检测器，3位乘法器，数字报表等-It contains from easy to difficult six very classic verilog example, a sequence detector, three multiplier, digital statements, and so on
aa
- 这个程序就是序列检测器的vhdl实现，真麻烦啊-This program is the sequence detector vhdl achieve real trouble
xuliefashengqi
- 序列发生器和检测器的verilog代码编写。-Sequence generator and sequence detector realization with verilog
sequence_detecter
- sequence detector based on system verilog
verilog-example
- verilog基础实验，包括篮球计数器，序列检测计等-verilog based experiments, including basketball counter sequence detector
serial1
- 基于VHDL语言实现的序列检测器，包含按键防抖动功能的实现。-Sequence detector based on the VHDL language, containing the button shake function to achieve.
The-VHDL-various-basic-code
- VHDL的各种基本代码 包括4选1,8选1多路选择器，8位全加器，加1减1计数器，序列检测器，异步清零16位加减可控计数器，数码管扫描程序，双2选1，状态机等基本程序！-VHDL basic code including 4 election 1,8 to 1 multiplexer selector, 8-bit full adder, plus 1 minus 1 counter sequence detector, asynchronous clear 16 plus or minus
11
- VHDL序列检测器，使用了EDA课程里面用到的状态机.-VHDL sequence detector, the use of EDA curriculum used inside the state machine.
SCHK
- ise13.2环境下VHDL编写的8位序列检测器+仿真波形-ise13.2 environment in VHDL 8 sequence detector+ simulation waveforms
seqdet_5
- 本程序是5位序列检测器的Verilog源代码,已经过上机运行检测。-This program is five sequence detector Verilog source code, has been detected on the machine running.
10010sequece-detector
- 序列发生器，Verilog HDL语言描述，包含文件说明和波形截图-Sequence generator, Verilog HDL language descr iption , contains the file descr iption and waveform capture
Seq_Det
- sequence detector in state machine
detseq
- verilog 序列检测器实例，检查输入数据中某一种序列是否出现-verilog sequence detector instance, check the input data, whether there is a particular sequence
Moore
- VerilogHDL语言实现的Moore 序列检测器-VerilogHDL language of Moore sequence detector
Mealy
- VerilogHDL语言实现的Mealy序列检测器-VerilogHDL language of Mealy sequence detector