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BPSK_Simulation_for_AWGN_Rayleigh_Channels
- BPSK SYSTEM SIMULATION We simulate the generation of random variables r0 and r1, which constitutes the input to detector.The detector output is compared with the binary transmitted sequence and an error counter is used to count the number of bit e
FSM
- 序列检测器，采用移位寄存器实现，检测特定序列“101011”-Sequence detector using a shift register implementation, detection of a specific sequence 101011
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- 基础实验_12_有限状态机 ：Moore型序列检测器-Basic experiment _12_ finite state machine: Moore type sequence detector
fsm
- verilog语言，有限状态机实现的序列检测器-verilog language, finite state machine sequence detector
bits
- verilog语言，移位寄存器实现的序列检测器-verilog language, to achieve the shift register sequence detector
examples
- Code on Debouncer, ripple carry adder, Sequence detector, huffmann encoder and some more examples in VHDL
s5
- 清华大学电子系 时序逻辑实验报告 包括：触发器设计，计数器设计，累加器设计，序列检测器设计/有限状态机实现-Tsinghua University, Department of Electronics, sequential logic test report include: trigger design, counter design, accumulator design, the sequence detector design/finite state machine
XuLie
- 序列检测机，可检测8位数字序列，米勒型状态机-Sequence detector can detect 8-digit sequence, Miller-type state machine
seqdet
- 基于verilog hdl的10010序列检测器。-10010 sequence detector based on Verilog hdl.
8_1
- 一个具有置位、复位、左移和右移功能的八位移位寄存器/“01011010”序列检测器。移位寄存器电路端口为：异步清零输入端口rst，输入时钟clk，置数判断输入端口load，移位类型判断输入端口m，数据输入端口data[7:0]，输出端口q[7:0]。序列检测器电路端口为：异步清零输入端口rst，输入时钟clk，串行数据输入端口d，输出标志端口s。(A eight bit shift register / 01011010 sequence detector with set, reset, le
序列检测器
- 本例子为一个序列检测器的程序，序列为：110010010000100101００，检测的序列为10010(This example is a sequence detector procedure, the sequence is: 11001001000010010100, the detection sequence is 10010)
DDSRF-PLL
- 本文论述了在控制的一个重要方面电网连接的电源转换器，即检测基波正序分量的电网电压不平衡和扭曲的条件下。明确地,提出了一种积极的基于一种新的序列检测器双同步坐标系的解耦锁相环（双dq–PLL），完全消除了检测误差传统的同步参考框架（SRF–锁相环PLL）。(This paper deals with an important aspect in the control of grid connected power converters, that is, detecting the fundam
用VHDL设计移位寄存器
- 实现序列检测，让你通过VHDL语言实现序列数字的发生(Sequence detector code)
kebenchengxu
- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，同步计数器，序列检测器的设计，序列信号发生器，一般状态机等等。(The small program of some textbooks. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3
1
- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3 prio
2
- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. It includes 3 line -8 line decoder, 4 selector 1 selector, 6 elevator, 8 line -3 encoder, 8 l
lab5_0131_micro
- matlab sequence detector
110序列检测器
- 110的序列检测器，添加了使能端检查其正确性(The sequence detector of 110 adds the enable end to check its correctness.)
6bit序列检测器
- 1、用数码管显示被检测的连续数字序列，MSB在前； 2、当输入的数字序列连续六个值等于一组串行码（如00011101）时输出高电平并报警显示，同时用两位数码管显示出现的次数。 3、串行码的值可设定(6bit sequence detector)
并网逆变器中全软件锁相环的设计与实现
- 讲述并网逆变器中全软件锁相环的设计与实现，，即检测基波正序分量的电网电压不平衡和扭曲的条件下。明确地,提出了一种积极的基于一种新的序列检测器双同步坐标系的解耦锁相环（双dq–PLL），完全消除了检测误差传统的同步参考框架（SRF–锁相环PLL）(and implementation of all software phase-locked loop in grid connected inverter is described, that is, detecting the positive a