搜索资源列表
EDA
- EDA实验序列信号检测器和模可变计数器，工程文件和VHDL文件-EDA test sequence signal detector and variable-counter model, project files and VHDL files
adc3
- take a input vector which is no of users of b[kx1] and code vector which will be a matrix now s=[Nxk],where then give to matched filter,non-correlating detector, by randomised sequence.-take a input vector which is no of users of b[kx1] and
adc4
- with channel, take a input vector which is no of users of b[kx1] and then give to matched filter,non-correlating detector, and non-adaptive mmse,see the results by hadamard by randomised sequence.
xu_lie_jian_ce_qi
- 本设计通过Moore状态机设计一序列检测计。当输入的序列含有预置的11100101序列中的正确顺序时，进入下一个状态，直到到达st8状态，一个序列检测完毕。值得注意的是，当输入为111100101时，检测计仍能检测出里面的11100101序列，同时，当一个序列检测完毕时，下一个序列的高位可以只含有两个11即输入为1100101时，检测计一样能检测一个正确的序列。-The design by Moore state machine to design a sequence of the detec
mealy_machine
- mealy_machine该代码为序列脉冲检测器当输入信号110时电路输出为1否则为0-mealy_machine the code sequence when the input signal pulse detector circuit 110 output is 1 0 otherwise
EDA3add
- 序列信号发生器与检测器设计：用状态机设计实现串行序列检测器的设计，先设计（可用原理图输入法）序列信号发生器产生序列：0111010011011010；再设计检测器，若检测到串行序列11010则输出为“1”，否则输出为“0”，并对其进行仿真和硬件测试。-Sequence signal generator and detector design: The Design and Implementation of a serial sequence of state machine design of
XLXH
- 完成序列为0111010011011010的序列生成器 2．用状态机设计实现串行序列11010的检测器 3. 若检测到符合要求的序列，则输出显示位为“1”，否则为“0” 4. 可对检测到的次数计数 -Complete sequence is 0111010011011010 sequence generator 2. State machine design using serial sequence of 11 010 detector 3. If the sequence i
seqdet
- 经典编码风格的序列检测器，综合效率高，很有学习价值。-Coding sequence of the classic style of the detector, integrated, high efficiency, great learning value.
work1
- 实现序列检测器的功能，检验序列代码是否正确，给出说明。-Detector to achieve the function of sequence to test serial code is correct, given instructions.
matlab
- 仿真程序：首先需要用一个随机发生器产生（0.1）内的均匀随机数，然后再将该序列映射到对应的幅度电平｛Am｝。然后将这个范围再分成4个相等的区间，这些子区间分别对应于4个信号比特的符号00，01，10，11。检测器观察到r=Am+n，并且计算r和4种可能传输的信号幅度之间的距离，它的输出Bm就是相应于最小距离的信号电平。Bm与真正的的传输信号幅度比较，差错计数器用来对检测器产生的差错计数。-Simulation program: first need to use a random genera
detect
- 基于QuartusII的序列检测器，可下载到实验箱-Based on the sequence QuartusII detector, can be downloaded to test me
DS-CDMA-with-PASTd-MUD-with-m-DS
- DS-CDMA链路中加入基于子空间的PASTd多用户检测方法。系统中采用m序列阔频，可以通过高斯信道或瑞利信道。可以直接运行得到不同信噪比下的误码率曲线。-DS-CDMA link added Subspace-based multiuser detector PASTd. M sequence used in the system wide-band, Gaussian channel, or by Rayleigh channel. Get different signal to noise
Program2
- 将8位待测预置数作为外部输入信号，即可以随时改变序列检测器中的比较数据。写出此程序的符号化单进程有限状态机。-The 8-bit pre-measured as the number of external input signal, which can change at any time in the sequence comparison of the data detector. Write the symbol of this process a single process fini
VHDL
- 1、根据设计要求，完成对序列信号检测器的设计。 2、进一步加强对QuartusⅡ的应用和对VHDL语言的使用。-1, according to design requirements, to complete the sequence of the signal detector design. 2, to further strengthen the Quartus Ⅱ applications and the use of the VHDL language.
sequential-detactor
- 本次例程包括七阶伪随机序列发生器、序列码检测器，奇偶校验器、CRC（循环冗余）校验器，并附有FPGA的代码和仿真。-The routines including seven order pseudo-random sequence generator, sequence yards detector, parity validator, CRC (cyclic redundancy) validator, and with FPGA code and simulation.
EDA1
- 用VHDL编程实现序列信号发生器与检测器设计和数字钟设计-VHDL programming sequence signal generator and detector design and the design of the digital clock
check
- 这是一个检测器，功能是可以检测输入信号里面“1111”序列的vhdl程序。-This is a detector, the function is the sequence of " 1111" of the input signal which can be detected vhdl procedures.
EDAexp4
- FPGA环境下，用VHDL语言实现序列脉冲器和检测器。-FPGA environment, the use of the VHDL sequence of pulses and detector.
seq_detector
- 3比特的任意二值序列检测器(例如101、110、001等)。从任意序列中检测出三比特的序列。包含VHDL源码以及testbench测试源码程序。-The 3-bit binary sequence of any detector (e.g., 101,110,001, etc.). A three-bit sequence is detected from an arbitrary sequence. Includes VHDL source code and testbench test so
Matlab-Source-Codes
- Generation of ASK: Amplitude shift keying - ASK - in the context of digital communication is a modulation process which imparts to a sinusoid two or more discrete amplitude levels 1. These are related to the number of levels adopted by the digit