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sine
- Verlog语言描述的正弦信号发生器的源代码可以方便的实现长生正弦信号-Language Verlog sinusoidal signal generator described in the source code can easily achieve the longevity of the sinusoidal signal
FPGA_VHDL_sinusoidal_function
- 该文件包含基于VHDL的正弦信号发生器的设计源码-This file contains the VHDL-based design of sinusoidal signal generator source code
sin
- QUARTUSS||环境下的简易正弦信号发生器的设计,VERILOG 代码,用到了嵌入式逻辑分析仪-QUARTUSS | | environment simple sinusoidal signal generator, VERILOG code, use the embedded logic analyzer