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verilog
- VERILOG设计实例，非常详细的例子，有交通灯，频率计，数字跑表等等例子
verilog
- 基于QUATEUS2的设计一个8位频率计verilog语言编程-The design is based QUATEUS2 an 8-bit frequency counter verilog programming language
counter
- verilog写的频率计程序的计数模块,-Verilog written procedures for counting frequency meter module,
cymometer
- 数字频率计的源码 最大测量频率达到30MHz-Digital frequency meter measuring frequency of the source code to achieve the maximum 30MHz
fre500000
- 等精度数字频率计的Verilog源码，从上到下的设计思路，分为6个模块。上过Altera公司的FPGA板。 供大家参考，希望大家不要照抄！-Such as precision digital frequency meter Verilog source code, from top to bottom of design ideas, divided into six modules. Been to Altera' s FPGA boards. For your reference, h
asias_dds
- 一个简易的信号源，具有多种波形发生功能还有扫频，调制，频率计等相关功能-My project is on Direct Digital Synthesiser using Verilog HDL.This project is doing by me on july 2009 in summer training at NIT Kurukshetra, India. This DDS system generate the square wave, Triangular wave,Sine wa
frequencycounter
- 一个简单大家容易看的懂的频率计设计程序，可以实现自动换挡功能。-A simple and easy to see to understand all of the frequency counter design program that can automatically shift feature.
Cymometer
- Verilog 编写的频率计，使用8位LED作为显示，Quartus II 6.0的工程文件。保证好用，EPM240T的芯片。使用了66 的资源。-Written in Verilog frequency counter, using 8-bit LED as the display, Quartus II 6.0 of the project file. To ensure easy to use, EPM240T chips. 66 of the resources used.
digital-frequency
- 数字频率计 采用Verilog语言编写，分为8个模块，分别是计数器，门控，分频，寄存器，多路选择，动态位选择，BCD译码模块-Digital frequency meter using Verilog language, divided into eight modules, namely, the counter, gated, frequency, register, multiplexer, Dynamic Choice, BCD decoding module
Fre_Counter_verilog
- 基于ep3c25的FPGA频率计的简单设计（用verilog HDL），直接打开即可-FPGA frequency counter based on ep3c25 of simple design (using verilog HDL), can directly open the ... ...
Digital_frequency_meter
- 本项目基于等精度测量频率的原理,利用Verilog硬件描述语言设计实现了频率计内部功能模块,对传统的等精度测量方法进行了改进,增加了测量脉冲宽度的功能 采用STC89C52单片机进行数据运算处理,利用液晶显示器对测量的频率、占空比进行实时显示。充分发挥FPGA(现场可编程门阵列)的高速数据采集能力和单片机的高效计算与控制能力,使两者有机地结合起来。-The project is based on the principle of equal precision frequency measure
cymometertiaoshi
- verilog语言编写的频率计代码，已经调试过，好使-verilog code written in frequency meter has been debugged, good
pinlvji
- 自己编的一个频率计，verilog语言写的，用数码管显示方波的频率，测量量程是0.1hz~9999999hz，测方波的稳定性极高。-Their series a frequency counter, verilog language written with the digital display of the square wave frequency, measurement range is 0.1hz ~ 9999999hz, high stability of the square w
verilogClassicSamples
- verilog常用程序及其仿真结果整理，包括LCD，LED，AD采集，URAT，电子琴，电梯控制，自动售货机控制，出租车计价器，电子时钟，频率计，MPSK调制与解调-verilog common finishing process and its simulation results, including LCD, LED, AD collection, URAT, keyboard, elevator control, vending machine control, taxi meter,
频率计
- Verilog和VHDL联合编写的频率计
asd
- 频率计，自动计算输入频率并二进制输出显示。(cymometer; frequency meter)
cymometer
- 使用XILINX公司出品FPGA开发板，基于verilog语言，实现简单的脉冲频率计功能；(The FPGA development board is produced by XILINX company, and a simple pulse frequency meter function is realized based on Verilog language.)
pinlvji
- 本文件用于测波形频率的verilog代码，是典型的数字频率计的源代码(This document is used to measure the frequency of the Verilog code, the source code of a typical digital frequency meter)
Verilog的135个经典设计实例
- Verilog的135个经典设计实例，部分摘录如下：【例 9.23】可变模加法/减法计数器【例 11.7】自动售饮料机【例 11.6】“梁祝”乐曲演奏电路【例 11.5】交通灯控制器【例 11.2】4 位数字频率计控制模块【例 11.1】数字跑表【例 9.26】256×16 RAM 块【例 9.27】4 位串并转换器【例 11.8】多功能数字钟【例 11.9】电话计费器程序【例 12.13】CRC 编码【例 12.12】（7，4）循环码纠错译码器【例 12.10】（7，4）线性分组码译码器【例