搜索资源列表
pong
- vga verilog codes which design a pong game and output to vga monitor
Altera_DDR_controller_core
- Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, descr iption documents, DDR verilog model and simulation testbench are all included.
i2c-verilog
- 可进行i2c读写操作I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable-it can write and read codes in i2c.I2C is a two-wire, bi-directional serial bus that provides a
ldpc_c_code
- LDPC码在基于BP (Belief Propagation) 的迭代译码相结合的条件下具有逼近Shannon 限的性能，是继turbo 码后在纠错编码领域又一重大进展。压缩文件中给出了LDPC在高斯信道下的c程序。-LDPC codes based on BP (Belief Propagation) Iterative Decoding of combining conditions with performance approaching Shannon limit on the heel
D_BLAST44
- MIMO 4*4系统D-BLAST编译码方案，利用ISE仿真环境，verilog编程实现。-MIMO 4* 4 system codec D-BLAST program, using ISE simulation environment, verilog programming implementation.
rs-codec(255-223)
- RS编码是一种纠错码，本程序实现RS（255，223）用FPGA 实现RS编码，程序在Quartus II中调试通过。-RS coding is an error-correcting codes, the procedures for the realization of RS (255,223) with FPGA realization of RS codes, in the Quartus II program through the debugger.
bpsk
- These code are some matlab codes for BPSK modulator and demodulator in fading channels for wireless communications
ac97controller
- ac`97 controller verilog codes-ac `97 controller verilog codes
fangzhen
- 卷积码和循环码的verilog编码以及仿真结果图，-Convolutional codes and cyclic codes and the coding verilog simulation results map
add_sub
- basu verilog codes for adder subtracor etc
key
- Verilog HDL编写的键盘扫描程序，考虑了判断按键弹起的问题。程序按一定的频率用低电平循环扫描行线，同时检测列线的状态，一旦判断有一列为低则表示有键被按下，停止扫描并保持当前行线的状态，再读取列线的状态从而得到当前按键的键码；等待按键弹起：检测到各列线都变成高点平后，重新开始扫描过程，等待下一次按键。-Written in Verilog HDL keyboard scanner, taking into account to determine key bounce problem. P
vani_tut
- A total of 52 files showing examples of shell scr ipting for Cadence NCSIM simulator, multiple single module + testbench examples in verilog 1995/2001, a "Randomized Smoothing Networks" paper (doc)+ppt+verilog codes and test bench from my EE7700 Dist
SDR
- FPGA based implementation of a SDR - codes in Verilog HDL for the processor and control.-FPGA based implementation of a SDR- codes in Verilog HDL for the processor and control.
NewFolder
- these are some verilog codes
83390078DDS
- DDS的工作原理是以数控振荡器的方式产生频率、相位可控制的正弦波。电路一般包括基准时钟、频率累加器、相位累加器、幅度/相位转换电路、D/A转换器和低通滤波器（LPF）。频率累加器对输入信号进行累加运算，产生频率控制数据X（frequency data或相位步进量）。相位累加器由N位全加器和N位累加寄存器级联而成，对代表频率的2进制码进行累加运算，是典型的反馈电路，产生累加结果Y。幅度/相位转换电路实质上是一个波形寄存器，以供查表使用。读出的数据送入D/A转换器和低通滤波器。-DDS works
cf_ldpc_latest.tar
- we need exactly a complete turbo codes in either MATLAB or VERILOG
DCTPROGRAM.ZIP
- it is verilog code for two dimentional dct
kuaisufuliyebianhuan_fft_lunwen
- 快速傅里叶变换FFT论文及有关的源程序代码，值得一下，不下实在是浪费了，我找了很久才找到的，有些是一些大牛的毕业论文全文-FFT，VERILOG，some article about FFT and some codes of FFT
viterbi
- This a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is w
sbiu_phase_1
- VHDL SYSTEM VERILOG CODES