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verilogzzhwfy
- 用Verilog实现QPSK中的差分,扰码,串并,解差分,解扰码,解串并,用MUXPLUS2进行仿真-QPSK with Verilog realize the difference, code, and serial, Xie difference, encryption codes, and solutions Series, The simulation used MUXPLUS2
hdlc
- 该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码，会用QUATUSII的人都应该知道如何使用，希望能给你带来帮助-The project is based on the language verilog hdl frame transmission protocol HDLC frame of this generation - Codes will be used QUATUSII people should know how to use, in the hop
verilog_code
- 這是一堆verilog的source code.包含許多常用的小電路.還不錯用.-many verilog source codes, include a lot of small electrocircuit.
hamming_encodeadecode
- 用Verilog语言编写的对m序列进行汉明码编译码的程序。具体实现为产生m序列后对其进行(7,4)汉明码编码并加错，然后将其纠错译码并输出，详细过程见仿真。-Written by Verilog m sequence of procedures for coding and decoding Hamming codes. Concrete realization of m sequence to produce its (7,4) hamming code and a mistake, and
minimigJ_source_04_08_2008
- Verilog, c and asm source codes of the Minimig system, a fpga implementation of the Amiga computer. Version minimig-j used on the Minimig fpga board.
Source_minimig_DE1_DE2_12e_new
- Verilog, VHDL, c and asm source codes of the Minimig system, a fpga implementation of the Amiga computer. Version minimig-de1/de2 used on the de1 and de2 fpga boards.
snapshot_ver1.26
- Verilog, VHDL, c and asm source codes of the Minimig system, a fpga implementation of the Amiga computer. Version c-one used on the c-one fpga board.
veri_adder
- verilog VHDL codes for adders
NewFolder
- these are the codes written in verilog which are for a dual elevator design
SwitchCheck
- 一个通用的SPI程序,由VERILOG语言编写。时钟由控制机提供，可以修改SPI的发送数据位数。-a SPI codes
ass1_2_hamming
- Hamming codes are a class of binary linear codes. They can detect up to two simultaneous bit errors, and correct single-bit errors. In particular, a single-error-correcting and double error detecting variant commonly referred to SECDED.-a) Develop a
finial_test
- 卷积码和Viterbi译码的源程序，在Xilinx ISE环境下使用Verilog编写，有助于卷积码和Viterbi译码的学习-Convolutional codes and Viterbi decoding of the source, in the Xilinx ISE environment, use of Verilog prepared to help convolutional codes and Viterbi decoding of the study
aes_encryption
- AES 加密算法, 可综合的 verilog代码-AES encryption algorithm, synthesizable verilog codes
16x 16 vedic mulbit
- vedic 16x16 design and teshbench fully working codes..
Chapter 4
- codes and simulation of chapter 4
Final
- u should upload 5 codes/documents
CODES+ISSS'07 Full Paper.pdf
- network on chip paper
2bit_ecc
- 基于BCH码的ECC纠错算法，可纠错2位错误码，供参考(Based on BCH code ECC error correction algorithm, two error codes can be corrected for reference.)
Verilog codes
- IT IS A CARRY S ELECT ADDER TO IMPROVE PERFORMANCE.
Assignment-2.2.tar
- verilog-HDL codes for different basic digital circuits elements