搜索资源列表
CRC.rar
- Verilog写的 CRC 编码 ,CRC code written in Verilog
A-PAINLESS-GUIDE-TO-CRC-ERROR-DETECTION-ALGORITHMS
- A PAINLESS GUIDE TO CRC ERROR DETECTION ALGORITHMS CRC校验理论与实践的经典教程，Ross写的。-A PAINLESS GUIDE TO CRC ERROR DETECTION ALGORITHMS CRC checksum of the classic theory and practice tutorials, Ross wrote.
crc
- 这是CRC字符串校验的源码，可对字符串校验后输出校验码-This is the CRC checksum of the source string can be output after the string checksum validation code
crc
- CRC校验码的实现，校验码6位，寄存器串行实现方式，经项目实际验证正确-CRC Check Code realization Check 6, register serial ways, the right to verify the actual project
CRC
- CRC和线性码程序 可能对初级学习有用 希望能够好好利用-CRC
crc
- CRC-16 VHDL Source Code
RFC_1622_CRC16_m
- RFC1662 CRC-16 table generation and CRC checking. Implemented in embedded matlab with scr ipt to test and enable c/c++ code generation. Useful fo check against VHDL/Verilog and other embedded systems to help generate test vectors.
CRC_outputlogic
- custom crc generater(verilog/vhdl)
crc
- verilog crc source code
CRC
- 循环冗余码实现，用Verilog语言实现的，希望和大家分享-CRC implementation, using Verilog language, and would like to share
crc-gen
- CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible
crc_verilog_xilinx
- 各类CRC效验码 有CRC8-8 CRC16-8 CRC32-8 CRC12-4 CRC-CCIT-8-CONTAIN CRC8-8 CRC16-8 CRC32-8 CRC12-4 CRC-CCIT-8
CRC
- CRC校验参考设计Verilog代码 包括所有代码-Verilog code for CRC check reference design includes all the code
CRC-Generator-for-Verilog-or-VHDL
- CRC Generator for Verilog or VHDL-CRC Generator for Verilog or VHDL
crc
- CRC编程源程序，使用Verilog硬件编程语言进行编程-CRC program source code, Verilog hardware programming language used to program
crc
- For implementing the CRC in verilog or VHDL
crc-gen[1]
- hamminag code using verilog this code is desinged for detecting
uvm-crc-test
- UVM简单例程，DUT为Verilog小程序。(UVM simple routine, DUT is Verilog applet.)
CRC
- crc校验的程序,关于crc的校验程序，8位转化为8位的并行算法，使用verilog编写的(crc search .12bit_4bit,8_8bit,and16 bit_8bit,32bit_8bit progranming by verilog languages,is very good. I think is correct)
Verilog的135个经典设计实例
- Verilog的135个经典设计实例，部分摘录如下：【例 9.23】可变模加法/减法计数器【例 11.7】自动售饮料机【例 11.6】“梁祝”乐曲演奏电路【例 11.5】交通灯控制器【例 11.2】4 位数字频率计控制模块【例 11.1】数字跑表【例 9.26】256×16 RAM 块【例 9.27】4 位串并转换器【例 11.8】多功能数字钟【例 11.9】电话计费器程序【例 12.13】CRC 编码【例 12.12】（7，4）循环码纠错译码器【例 12.10】（7，4）线性分组码译码器【例